category: Top Stories

category: Auto, Security & Edge AI

Executive Insight: Simon Segars
By Ed Sperling - 03 Jun, 2014 - Comments: 0

SE: What concerns you most? Segars: In the context of design and where chip design is going, ARM is a long-term business. We’re doing stuff now that is going to ship in five years’ time. Obviously, for everyone in this space, Moore’s Law has been a fantastic thing. It’s enabled us to achieve really fantastic scaling of transistors, and everyone knows that is getting harder and harder... » read more

Easing The Path To Evolution
By Ann Mutschler - 29 May, 2014 - Comments: 1

On the surface, revolutionary changes in EDA seem unlikely due to the risk of replacing costly tools, flows and methodologies. But are they really? The answer depends on whom you ask. For Part One, click here. Risk is a big part of the equation here. “There are always pioneers in an organization and what you need to do is find someone who is willing to take some risk and typically it’s o... » read more

Executive Insight: Hossein Yassaie
By Ed Sperling - 28 May, 2014 - Comments: 1

SE: What concerns you looking out at the semiconductor industry? Yassaie: There are big changes in the industry over the last two years, such as the verticalization in the mobile space. Every semiconductor company wanted to play in mobile. It was just a fact of life that some of these guys would give up. That was a major change, and it was something we could see coming. Our focus is diverse ... » read more

What’s Wrong With Power Signoff
By Ed Sperling - 12 May, 2014 - Comments: 0

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Pointing Fingers, Often In The Wrong Direction
By Ed Sperling - 08 May, 2014 - Comments: 0

Every design these days, regardless of whether it’s a processor, an SoC, an ASIC, FPGA or stacked die, relies on a combination of re-used and third-party intellectual property. No company—not even Intel, Apple or Samsung—has the capability of building everything itself within a highly compressed market window. There is a spectrum of IP use and re-use, of course. In some cases, it may i... » read more

IP To Meet 2.5D Requirements
By Ann Mutschler - 08 May, 2014 - Comments: 1

The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon. “The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASIC... » read more

Improving LP Verification Efficiency
By Ann Mutschler - 08 May, 2014 - Comments: 1

The addition of low power circuitry can create so many corner cases that many can escape even the best-written testbenches. This has driven the need for so many additional verification cycles to be run that there must be many datacenter managers at semiconductor companies wondering if it is a trick by the power companies to cause an equal amount of power to be consumed by low-power verification... » read more

Can HLS Be Trusted?
By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Powerful Memories
By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

Executive Insight: Charlie Cheng
By Brian Bailey - 23 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with Charlie Cheng, CEO of Kilopass Technologies, to talk about his role in transforming the company. What follows are excerpts of that conversation. SE: Can you talk about your existing product and its evolution? Cheng: The founders discovered a new type of [Non Volatile (NVM), One Time Programmable (OTP)] memory and protected it with a number of patents.... » read more

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