category: Top Stories

category: Auto, Security & Edge AI

High Level Synthesis Grows Up
By Brian Bailey - 13 Mar, 2014 - Comments: 2

When Semiconductor Engineering proposed this Experts At The Table discussion, which was held at the recently concluded DVCon, [getentity id="22032" e_name="Cadence"] had yet to express its intention to purchase [getentity id="22087" e_name="Forte"]. Little did we know that the stakes in the [gettech id="31015" comment="high-level synthesis"] (HLS) arena were being raised so high. Is this an in... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Pointing Fingers In Verification
By Brian Bailey - 12 Mar, 2014 - Comments: 11

With most EDA tools, the buying decision is related to improved quality of results or increased productivity. Will a new synthesis or clock optimization tool enable designers to do more, faster and are those gains worth the price? The equation is fairly simple. When it comes to verification tools, things are more complex. You can still make productivity gains, or purchase an additional tool ... » read more

SoC Integration Mistakes
By Ed Sperling - 10 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

Reducing And Optimizing Power
By Ann Mutschler - 03 Mar, 2014 - Comments: 0

While power optimization/reduction techniques such as clock gating do help engineering teams improve designs from a power perspective, more can be done. In fact, there are tools and methodologies under development to incorporate power in a more meaningful way. Part of that involves accurately pinpointing what designers should be looking for. “If you look at academia or research that has... » read more

SoC Integration Mistakes
By Ed Sperling - 26 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. S... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Executive Insight: Kathryn Kranen
By Ed Sperling - 17 Feb, 2014 - Comments: 0

Semiconductor Engineering sat down with Kathryn Kranen, president and CEO of Jasper Design Automation, to discuss what's changing in the semiconductor industry, why that's happening, and what to watch out for. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you up at night? Kranen: Figuring out ways to... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 14 Feb, 2014 - Comments: 4

In 2004, Intel introduced a new line of Pentium chips that ran at 3.6GHz. Fast forward to today, and the company’s i7 processors run at 3.5GHz with a Turbo Boost to 3.9GHz. There have been many improvements in the meantime. There is more cache and dramatically faster access to data stored in that cache. And there are more cores with improved coherency between them. But the big problem is p... » read more

Do Chips Really Work The First Time?
By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

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