category: Top Stories

category: Auto, Security & Edge AI

Best Options For Using AI In Chip Design
By Ed Sperling - 20 Aug, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency
By Liz Allan - 31 Jul, 2025 - Comments: 0

Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI's power consumption. Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-so... » read more

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

How AI Will Impact Chip Design And Designers
By Ed Sperling - 31 Jul, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the role and impact of AI in chip design with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir Arora, head of engineering... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Startup Funding: Q2 2025
By Jesse Allen - 14 Jul, 2025 - Comments: 0

Investors were drawn to a wide range of innovative approaches in Q2 2025, backing startups developing superconducting logic, chips for an emerging number format, big data processors, and novel power semi architectures. At the same time, photonics continues to draw investment dollars due to its ability to move data faster and with less energy at both the chip-to-chip and data center levels. T... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Distributing Intelligence Inside Multi-Die Assemblies
By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

EDA’s Top Execs Map Out An AI-Driven Future
By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

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