category: Top Stories

category: Auto, Security & Edge AI

IP Verification Challenges
By Brian Bailey - 30 Jul, 2015 - Comments: 0

At the Design Automation Conference this year, the Designer and IP tracks were the stars of the show in many ways. These sessions catered to industry rather than academia and provided engineers with information they could directly use in their jobs. Many of the sessions were filled to capacity and Anne Cirkel, general chair for the 52nd DAC, was enthusiastic about the growing success of these t... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 27 Jul, 2015 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to talk about the effects of industry consolidation, China's impact, and the unfolding security threat with the IoT. What follows are excerpts of that interview. SE: Consolidation is one of the big stories right now. What does that mean for your company and the industry as a whole? Pierce: It's a very inter... » read more

The Future Of Moore’s Law
By Ed Sperling - 22 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Charlie Cheng, CEO of [getentity id="22135" e_name="Kilopass Technology"... » read more

The Future Of Moore’s Law
By Ed Sperling - 29 Jun, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

What Is A System Now?
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

Defining a system used to be relatively straightforward. But as systems move onto chips, and as those chips increasingly are connected with applications and security spanning multiple devices, the definition is changing. This increases the complexity of the design process itself, and it raises questions about how chips and software will be designed and defined in the age of the [getkc id="76... » read more

Wrong Verification Revolution Offered
By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

Asynchronous’ Impact On Tools
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

In the right situation, using asynchronous logic makes a lot of sense—especially for security and IoT. But moving into the asynchronous design involves making tradeoffs, figuring out how the technical requirements of an application will impact the design, and understanding the limits of EDA tools in this area. “It's going to be halfway between digital and analog support,” said Bernard ... » read more

Full Coverage Or Full Monty
By Brian Bailey - 22 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

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