category: Top Stories

category: Auto, Security & Edge AI

Full Coverage Or Full Monty?
By Brian Bailey - 09 Jun, 2015 - Comments: 0

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Executive Insight: Charles Janac
By Ed Sperling - 08 Jun, 2015 - Comments: 0

SE: One of the big stories these days is consolidation. What are you seeing on your side? Janac: There are about 230 companies doing SoCs right now. Maybe 150 should be doing that. As the game gets more expensive and more difficult, some of the companies that don't have volume may have to do something else. Consolidation is part of that. But you're also going to see movement toward platforms... » read more

Emulation for Power
By Ann Mutschler - 01 Jun, 2015 - Comments: 0

Solving power problems in today’s leading-edge SoCs requires not only the best architectural choices but advanced tools and techniques to determine the right path to take. This equates to a combination of hardware emulation and power analysis/optimization software tools. Design teams today must have real-life scenarios to accurately predict the power impact of their architectural decisions... » read more

What’s Different At 16/14nm?
By Ed Sperling - 28 May, 2015 - Comments: 0

Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Memory Design At 16/14nm
By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

The Interconnect Bottleneck
By Ann Mutschler - 28 May, 2015 - Comments: 0

With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

Full Coverage Or Full Monty
By Brian Bailey - 28 May, 2015 - Comments: 1

Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Executive Insight: Jack Harding
By Ed Sperling - 28 May, 2015 - Comments: 0

SE: What's changed over the past 12 months? Harding: My starting point these days is around consolidation. At last count there were about 85 companies in the semiconductor industry. My bet is that at this time next year there will be about 70. The size of deal will not matter. Nothing will be too big. The strategic question is whether you're playing musical chairs and when the music stops, ... » read more

Problems Ahead for EDA
By Brian Bailey - 19 May, 2015 - Comments: 0

Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Problems Ahead For EDA
By Brian Bailey - 06 May, 2015 - Comments: 2

Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

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