category: Top Stories

category: Auto, Security & Edge AI

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Do Students Need More Formal Education?
By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 21 Nov, 2013 - Comments: 1

Semiconductor Engineering sat down with Jim Hogan, long-time industry venture capitalist; Simon Bloch, senior director at Samsung Electronics; Sumit DasGupta, formerly Si2 senior vice president of engineering; and Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What... » read more

Cracking The Tough Nut Using Formal Methods
By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Executive Viewpoint: Atoptech’s Jue-Hsien Chern
By Brian Bailey - 13 Nov, 2013 - Comments: 0

What is the difference between skyscrapers and chips? Dr Chern has worked on both and he says it’s all about how you apply margins. Jue-Hsien Chern started his technology career earning a M.S. and B.S. in Engineering from National Taiwan University and majored in structural engineering — bridges, dams, tunnels and high-rise buildings, all of which had to withstand earthquakes. That is a ... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 04 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: Debug
By Ed Sperling - 31 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy