category: Top Stories

category: Auto, Security & Edge AI

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

Power Impacts On Advanced Node IP
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

New Incentives For Lowering Power
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Despite all the focus by design teams on lowering power over the past few years, in many applications power is still the last consideration for many companies in the power-performance-area equation. That’s beginning to change, however, even for applications that in the past have not been particularly power-sensitive. There are several reasons for this shift. No. 1 on the li... » read more

The Essential Tool Kit
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Is there an essential chip design tool kit today that has only the ‘must haves?’ Sure, this sounds like a straightforward question, but the answer really depends on what process node the design will be manufacturing on. According to Jon McDonald, technical marketing engineer for the design and creation business at Mentor Graphics, there’s actually nothi... » read more

The New Mixed-Signal Flow
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler We are on the cusp of the mixed-signal era. Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, no longer are sufficient. They lead to excess iteration and prolonged design cycle time. Today’s mixed-signal designs require a new approach that enables design teams to be as efficient as possible productivity... » read more

The Growing Confidence Gap In Verification
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling It’s no surprise that verification is getting more difficult at each new process node. What’s less obvious is just how deep into organizations the job of verifying SoCs and ASICs now extends. Functional verification used to be a well-defined job at the back end of the design flow. It has evolved into a multi-dimensional, multi-group challenge, beginning at the earliest st... » read more

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

Quantum Shifts
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling Intel, STMicroelectronics and some of the leading memory providers already are working on 10nm process technology, and advanced researchers in universities and industry-leading companies are looking at 7nm, 5nm and even beyond. Those who have glimpsed this technological future have similar observations. There is no single technology problem that has to be solved at these node... » read more

Challenges Grow For EUV
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus In the late 1990s, a group led by Intel launched a consortium to propel extreme ultraviolet (EUV) lithography into the mainstream. Originally, the consortium, dubbed the EUV LLC, envisioned the advent of EUV scanners that would move into production at the 65nm node. Clearly, the now-defunct consortium underestimated the difficulties and challenges associated with EUV. ASM... » read more

Beam Me Up
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus For years, electron-beam tools have been struggling to keep up with photomask complexity, causing an alarming increase in write times and mask production costs. Intel and others recently warned that e-beams soon could reach their fundamental limits, thereby requiring the need for new solutions. And in the multiple patterning era, mask makers could see their capital costs soa... » read more

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