category: Top Stories

category: Auto, Security & Edge AI

Behind The Mask
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the current and future photomask manufacturing challenges with Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks, one of the world’s largest merchant mask makers. SMD: The outlook for the photomask industry is for 2% growth in 2012. Do you agree with that? Kalk: That’s ... » read more

Mask Repair Enters The Spotlight
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus For years, the biggest challenges in photomask manufacturing have revolved around the slow write times for electron-beam tools and soaring mask inspection costs. Now, photomask repair, a sometimes forgotten technology in the mask shop, is in the spotlight and turning into the clash of the titans. Mask repair involves the process of finding defects on a photomask and repairin... » read more

Deep Inside Intel
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

Transitioning States
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler While the concept of finite state machines is mature, understanding their role in design, the transitions between them and how to verify them are fundamental to managing power in today’s large SoCs. In essence, a finite state machine is a set of inputs and outputs and gate bits that describes the operation of the system. “Transitions happen from one state to... » read more

Design For Power
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more

CPU Architectures Get Specific
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler SoC and system design is already complicated, but as complexity continues to rise the industry must determine how to maintain sensitivity to power and cost and performance in the CPU architecture. Where does this stand today—not just with architectures and microarchitectures for consumer electronics but all other kinds of applications? What kinds of changes... » read more

The Increasing Challenge Of Reducing Latency
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling When the first mainframe computers were introduced the big challenge was to improve performance by decreasing the latency between spinning reels of tape and the processor—while also increasing the speed at which the processor could crunch ones and zeroes. Fast forward more than six decades and the two issues are now blurred and often confused. Latency is still a drag on per... » read more

Executive Briefing: Aart de Geus
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler EDA, IP, semiconductors, electronics…actually every industry is woven into the tapestry of a global macroeconomic system. Running a business successfully within this environment requires a unique skillset; at once entrepreneurial as well as wise and discerning. System-Level Design sat down with Aart de Geus, chairman and co-CEO of Synopsys, to discuss these iss... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy