Increase LVS Verification Productivity In Early Design Cycles


With the innovative Calibre nmLVS-Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. To read more, click here. » read more

Formal Solutions For SystemC/C++ Verification


OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

5G NR Primer For Amplifier And Filter Design


This primer examines some of the challenges engineers face when designing filters and power amplifiers for 5G New Radio (NR) communication systems. See how the Cadence AWR Design Environment platform can be used to simulate amplifier and filter performance under 5G operating conditions. Click here to continue reading.     » read more

Monte Carlo Analysis Using Synopsys Custom Design Platform


In this 5th video of the series, Kai Wang, Director of Engineering at Synopsys, explains the need of Monte Carlo to improve yield, and how designers use advanced features like variation scoping and sigma amplification to avoid costly MC simulations. Click here to watch this video white paper. » read more

How The Special Snowflake Problem Impacts Asset Management—And What You Can Do


Asset managers face ongoing pressure to maximize the reliability and efficiency of their installations. Monitoring a single site is challenging enough, but when management spans two or more sites, additional complexities are typically introduced. The core problem? No two sites are the same. They differ not only in geographic location, but also usually in age, schematic configuration, maintenanc... » read more

Process Model Calibration: Building Predictive And Accurate 3D Process Models


The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Survey: 2019 eBeam Initiative Perceptions Survey Results


Results of the 2020 eBeam Initiative Perceptions survey, now called the Luminaries survey, will be made available starting on September 22 here: Meanwhile, here is the 8th Annual Perceptions Survey – 2019 (July). 68 luminaries across 42 different companies participated. Some highlights: Deep learning impact predicted by 2020: 76% of the respondents say it’s somewhat to very lik... » read more

Efficient Sensitivity-Aware Assessment Of High-Speed Links Using PCE And Implications For COM


This technical white paper, originally presented at DesignCon, investigates the challenges of increased data rates and reduced margins in high-speed link design. Section 1: Introduction Section 2: State of the Art Link Evaluation and Assessment of Parameter Variability Section 3: Proposed Modeling Framework Section 4: Sensitivity Analysis of a High-Speed Interconnect Section 5: Conclusio... » read more

How ML Enables Cadence Digital Tools To Deliver Better PPA


Artificial intelligence (AI) and machine learning (ML) are emerging as powerful new ways to do old things more efficiently, which is the benchmark that any new and potentially disruptive technology must meet. In chip design, results are measured in many different ways, but common metrics are power (consumed), performance (provided), and area (required), collectively referred to as PPA. These me... » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation


Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

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