Outlook 2024: An Ever Growing Imperative


Sustainability is an ever-present and growing imperative. As an industry, we are at the forefront of the drive to innovate towards this goal. We must also accept the challenge of creating these high-performance, high added-value products using sustainable processes and practices. There is constant pressure to use energy and materials as efficiently as possible without compromising the quality a... » read more

Machine Learning Based MBIST Area Estimation


Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic me... » read more

Challenges Facing The Automotive Industry Now And In The Future


The next decade may be the most exciting for the automotive industry, with carmakers, suppliers, and consumers all witnessing changes and advancements coming at breakneck speed. In fact, there will likely be more development of new technologies to power vehicles, make them safer and offer more conveniences and services in the next 10 years than in the previous 50 years. Battery-electric powertr... » read more

Extending Design Technology Co-Optimization From Technology Launch To HVM With Calibre Fab Solutions


As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techni... » read more

Field Testing In 5G NR


5G NR network coverage measurements will be beam-based instead of cell-based. This will change the methodology of coverage KPI calculation. The amount of reference signals in the air is increasing as there will be multiple reference beams per cell, posing more stringent performance requirements for scanning receivers and test UEs. Both test UEs and scanners will be needed for 5G NR field verifi... » read more

System-Driven PPA For Multi-Chiplet Designs


As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Accelerated Optimization With IC Compiler II


Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. Click here to read more. » read more

A Configurable Test Infrastructure Using A Mixed-Language And Mixed-Level IP Integration IP-XACT Flow


This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation. Authors Erwin de Kock (NXP), Jos Verhaegh (NXP) and Serge Amougou (Arteris) describe: A configurable and reusable test infrastructure for RTL designs as an application of mixed-level and mixed-language integration using the IP-XACT stand... » read more

A Flexible Cluster Tool Simulation Framework With Wafer Batch Dispatching Time Recommendation


The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulatio... » read more

Important Process Parameter And Its Sensitivity Check By Virtual Fabrication: Channel Hole Profile Impact On Advanced 3D NAND Structure


A virtual DOE-based process sensitivity check was performed for two tiers of channel holes in a 3D NAND device. The channel hole tilt distance, twist angle, and their sensitivities to the visible area in silicon-oxide-nitride-oxide (SONO) punch process were analyzed. The results show that controlling the upper tilt distance is more important for offering a larger visible area. Also, a negative ... » read more

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