DDR Memory Test Challenges From DDR3 to DDR5


Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power requirements, higher density for more memory storage, and faster transfer speeds are constant. Servers drive the demand for next-generation DDR. Consumers benefit when existing and legacy generati... » read more

64-Bit RISC-V Microprocessor Delivers New Options For IoT Edge Development


Global and rapidly expanding IoT edge devices are becoming increasingly important for connecting various sensors to the cloud via networks. IoT edge devices are progressively integrating 64-bit microprocessors capable of running Linux and similar high-performance operating systems. Moreover, recent import and export regulation changes have produced a need for choices in CPU architecture for mic... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication


BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Services Beyond Packaging, Summer 2022 Newsletter


Technology Focus: Services Services Beyond Packaging: QP Technologies is known for offering a wide range of package types. We also provide a variety of semiconductor manufacturing services to meet your packaging and assembly requirements. These include wafer preparation (backgrinding, dicing, die sort and inspection), IC assembly processes for a variety of package types and materials, laser ... » read more

Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs


Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrat... » read more

Interactive Point-To-Point Resistance Simulations


Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

Preparation Of Geometry Models For Mesh Generation And CFD


Making geometry models suitable for CFD meshing is a time-consuming bottleneck in CFD analysis. We will discuss why and ways to fix the problems. Click here to read more. » read more

A New Era For HPC-Driven Engineering Simulation


Market pressure and technological advancements have rapidly changed the way engineers work. Design engineers increasingly work with larger and more complex models, must conduct more frequent simulation analysis, and iterate more rapidly. Compute constraints, however, often result in engineers limiting model sizes and simulation fidelity, or relying on lengthy, overnight simulation runs. ... » read more

Keyword Transformer: A Self-Attention Model For Keyword Spotting


The Transformer architecture has been successful across many domains, including natural language processing, computer vision and speech recognition. In keyword spotting, self-attention has primarily been used on top of convolutional or recurrent encoders. We investigate a range of ways to adapt the Transformer architecture to keyword spotting and introduce the Keyword Transformer (KWT), a fully... » read more

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models


Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied that often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates ... » read more

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