Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.
[youtube vid=UGkpCtRdZJ0]
» read more
System-Level Design talks with Mentor Graphics, Cadence, and an Accellera member about what's changing in verification--and where the missing pieces are.
[youtube vid=alb3dncca4o] » read more
System-Level Design digs into the future of the design automation tools industry and the Design Automation Conference with Cadence's Neil Hand, Atrenta's Mike Gianfagna and Springsoft's Johnson Teng.
[youtube vid=IYA2o0tzOZs] » read more
System-Level Design talks with Bob Bluth of the Naval Postgraduate School about UAV design and debug challenges--and what's inside of these devices. (The blue and green cellophane tape seal some of the access points prior to delivery--and the directions).
[youtube vid=wTsehbWwC8o] » read more
Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm.
[youtube vid=2wTj3EvRIRw]
» read more
Simon Segars, ARM's executive vice president and general manager of the company's physical IP group, talks about the war with Intel and which markets it's likely to affect.
[youtube vid=EISi5qpY77M] » read more
One-On-One with IDT CEO Ted Tewskbury: How IDT is bridging the analog and digital engineering worlds with a mixed-signal team approach.
[youtube vid=TRfJ5a3WJrw] » read more
Pixim's CEO talks about what the company outsources, what it keeps internal, and how it differentiates from the competition.
[youtube vid=jDoaQ91QM3c] » read more
Synopsys CEO Aart De Geus sounds off about the future of design and where growth will come from in the EDA market.
[youtube vid=GO-9ILL9fDg] » read more
A look at what's driving Cadence's new EDA 360 strategy, the problem areas in EDA and why the company decided to buy Denali.
[youtube vid=zreEWGsCe5A] » read more
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.
InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
This website uses cookies to improve your experience while you navigate through the website. The cookies that are categorized as necessary are stored on your browser as they are essential for the working of basic functionalities of the website. We also use third-party cookies that help us analyze and understand how you use this website. We do not sell any personal information.
By continuing to use our website, you consent to our Privacy Policy. If you access other websites using the links provided, please be aware they may have their own privacy policies, and we do not accept any responsibility or liability for these policies or for any personal data which may be collected through these sites. Please check these policies before you submit any personal information to these sites.
Necessary cookies are absolutely essential for the website to function properly. This category only includes cookies that ensures basic functionalities and security features of the website. These cookies do not store any personal information.
Any cookies that may not be particularly necessary for the website to function and is used specifically to collect user personal data via analytics, ads, other embedded contents are termed as non-necessary cookies. It is mandatory to procure user consent prior to running these cookies on your website.
