Chip Industry Technical Paper Roundup: Apr. 22

GenAI for analog; water immersion cooling; 2D materials roadmap; stochastic computing ReRAM; sub-10nm nanogap; pre-silicon HW trojans; C2RAM on FDSOI; cache coherence traffic for NoC routing; HW IP protection.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Generative AI for Analog Integrated Circuit Design: Methodologies and Applications McMaster University
The 2D Materials Roadmap Chinese Academy of Sciences, TU Denmark, Pennsylvania State University, University of Manchester, University of Cambridge et al.
Thermally Conductive Electrically Insulating Electronics Packaging for Water Immersion Cooling University of Illinois, Urbana, University of Arkansas and UC Berkeley
All-in-Memory Stochastic Computing using ReRAM TU Dresden, Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Case Western Reserve University, University of Louisiana at Lafayette and Barkhausen Institut
A progressive wafer scale approach for Sub-10 nm nanogap structures Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology
A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans Sandia National Laboratories
An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures Forschungszentrum Jülich, RWTH Aachen University and SOITEC
Learning Cache Coherence Traffic for NoC Routing Design Nanyang Technological University
HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction University of Florida

Find more semiconductor research papers here.



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