Chip Industry Technical Paper Roundup: Feb. 18

Warpage in wafer-level packaging; NVM tutorial; GAAFETs; uncore frequency scaling for heterogeneous systems; simulation of vertically stacked 2D Nanosheet FETs; rowhammer mitigation; thermal radiation; energy efficiency in RISC-V.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Modeling and Simulating Emerging Memory Technologies: A Tutorial TU Dortmund, TU Dresden, KIT and FAU ErlangenNürnberg
Exploring Uncore Frequency Scaling for Heterogeneous Computing University of Illinois Chicago and Argonne National Laboratory
First Demonstration of High-Performance and Extremely Stable W-Doped In2O3 Gate-All-Around (GAA) Nanosheet FET Georgia Institute of Technology and Micron
Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies Arizona State University
Simulation of Vertically Stacked 2-D Nanosheet FETs Università di Pisa and TU Wien
Securing DRAM at Scale: ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns KAIST and Sk hynix
High-Temperature Strong Nonreciprocal Thermal Radiation from Semiconductors University of Houston, California Institute of Technology and University of Wisconsin-Madison
Optimizing Energy Efficiency in Subthreshold RISC-V Cores Norwegian University of Science and Technology (NTNU)

Find all technical papers here.



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