Chiplet-compatible RISC-V; HI for HPC; photonic in-memory computing; defect inspection, characterization; CXL cache coherence; SoC security verification; nanosheet FETs for M3D integration; energy analysis 2D/3D architectures.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package | ETH Zurich and University of Bologna |
| Heterogeneous Integration Technologies for Artificial Intelligence Applications | Georgia Tech |
| Integrated non-reciprocal magneto-optics with ultra-high endurance for photonic in-memory computing | UC Santa Barbara, University of Cagliari, University of Pittsburgh, AIST and Tokyo Institute of Technology |
| Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review | KU Leuven and imec |
| Formalising CXL Cache Coherence | Imperial College London |
| A Survey on SoC Security Verification Methods | University of Florida |
| High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling | The University of Tokyo and Nara Institute of Science and Technology |
| Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Design | Cornell University |
| Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors |
KAIST, NYU, Brookhaven National Laboratory, and National Institute for Materials Science |
More Reading
Chip Industry Week In Review
Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion.
Technical Paper Library home
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