Don’t miss Fully-Depleted Tech Symposium during IEDM (SF)

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium.

As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s been doing these symposia during major conferences for going on four years now, and lively debates always ensue.

(Courtesy: Hilton Hotels & Resorts)

This next FD Tech symposium happens the first day of the IEEE’s IEDM conference in San Francisco – Monday, December 10^th at 8:15pm. Conveniently, it’s also taking place in the same building – at the SF Hilton.

Top technologists from STMicroelectronics, ST-Ericsson, IBM, ARM, Altera, LETI, Soitec, MEMC and others will be debating comprehensive Fully-Depleted Technology solutions.

But perhaps most importantly, we’re going to get the first product-level benchmarking results of 28nm FD-planar for mobile SoC and FPGA applications.  That’s silicon proof straight from the companies who are doing it.

If you’ve been following recent ASN postings from STM, ST-Ericsson, IBM and others, you know these folks are really excited about the results they’re seeing.

Here’s a peak at the presentations planned for the symposium:

• Planar Fully-Depleted Technology at 28nm and below for extremely power-efficient SoCs:  SoC level 28nm Planar Fully-Depleted silicon results
  By Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics
• Evaluation and benchmarking of 14nm planar Fully-Depleted Technology for FPGAs
  By Jeff Watt, Ph.D. Fellow, Technology Development, Altera Corporation
• Challenges and comparisons of designing power-efficient SoCs with planar Fully Depleted transistors and FinFETS
  By Rob Aitken, ARM Fellow
• Second-generation FinFETs and Fin-on-Oxide
  By Ed Nowak, IBM Distinguished Engineer and Device Chief Designer, Semiconductor R&D Center, IBM Systems and Technology Group

The presentations will be followed by a Q&A.

Admission is free, but space is limited, so you must reserve in advance – click here to go to the special registration site.

To recap, it’s the:

Fully-Depleted Transistors Technology Symposium
Hilton San Francisco Union Square Hotel (333 O’Farrell St.)
Monday, December 10^th, 2012
8:15pm to 10:30pm

Food & refreshments will be provided.

We won’t all be in San Francisco, so if you can’t get there, the presentations will be posted on the SOI Consortium website (you can also get the presentations from previous events there, too, as well as excellent white papers).

If you do go and want to share your reactions on Twitter, use #FDchipTech and @soiconsortium.

This will be a great event – don’t miss it!

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