Expanding Ecosystem Drives Automotive Semiconductor Gold Rush

Automotive chips have been around for more than 40 years. Why all the excitement now?

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Semiconductor chips designed to support automotive applications have been around for more than 40 years, a very long time in the technology business. These chips have been developed by semiconductor integrated device manufacturers (IDMs), who control every step of the design, manufacturing, test, qualification, reliability and quality aspects of these automotive chips. On top of that, special semiconductor processes have been needed to realize some of these chips. For example, a high-voltage process is needed for electronics that must survive a load dump and high-temperature operations inside the engine compartment. In addition, various locations in the chassis require chips that can work reliably up to 150°C ambient temperature (~175°C junction). Classic products include Insulated Gate Bipolar Transistors (IGBTs) for high-current switching, engine control units (ECUs) for emission controls, and embedded memory in microcontrollers for anti-lock braking systems (ABS), etc.

So why the hoopla about automotive SoCs in the past two or three years? The reasons are multifaceted and compelling: Tesla and artificial intelligence, vision processing and image recognition, miniaturization of sensors and in-vehicle networking, applications processors and in-vehicle infotainment, and active noise “manipulation” in modern high-end vehicles.

When Tesla introduced the Model S, it sent shock waves through the automotive supply chain. With its beautiful LCD screen replacing the clutter in the cabin, to wireless connectivity built into the car for remote software maintenance and update, to a slew of automated features that were practically rocket science. These features include adaptive cruise control, lane departure monitoring, lane departure mitigation, collision avoidance systems, automatic emergency breaking (AEB), automated parking, 360˚ surround-view cameras, and extensive use of sensor fusion to make all these capabilities a reality. Not to mention that it is a beautiful and very fast car. On top of that, all the smart semiconductors used were either borrowed from mobile application processor know-how or invented from scratch in Silicon Valley. The result is the accelerated development and deployment of similar systems in other brands of vehicles, with automotive SoC support coming from young startups to established chip makers with little automotive experience moving into this space. And hence the gold rush is on!

In-vehicle networking can be done in 40nm. Infotainment SoCs will need 28nm performance. ADAS systems will need 16nm, especially if they must run neural network algorithms. Foundry processes must be tuned to support higher temperature, long-term reliability and meet functional safety standards. IP enablement and ecosystem support must be in place to provide the necessary building blocks to realize these complex SoCs.

At the TSMC OIP 2017 event held in Santa Clara on September 13, TSMC announced 16FFC standard cell libraries and memories that meet AEC-Q100 and ISO 26262 requirements. TSMC also promoted the TSMC9000A program to ensure that any IP designed for automotive will meet the program criteria.

Just prior to the event, Cadence announced a comprehensive automotive IP portfolio for TSMC 16FFC. This broad IP portfolio enables a host of applications spanning in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems, and is registered in the TSMC9000A program. The comprehensive IP portfolio incorporates the key IP needed to implement advanced infotainment and ADAS SoCs and includes the Cadence flagship 4266-speed grade LPDDR4/4X DDR PHY and controllers and PCI Express 4.0/3.0 PHY and controllers. This is complemented by subsystems supporting MIPI D-PHY, USB 3.1/2.0, DisplayPort, Octal SPI/QSPI, UFS and Gigabit Ethernet with TSN. To support cost-effective automotive SoC designs, Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs. Cadence IP is designed to be ASIL-B ready and ASIL-C/D capable based on end users’ safety goals and safety requirements as outlined in the ISO 26262 standard.

For more information on the Cadence automotive IP portfolio, see https://ip.cadence.com/automotive.