Ferroelectric Memories Answer Call For Non-Volatile Alternatives

As system designers seek to manipulate larger data sets while reducing power consumption, ferroelectric memory may be part of the solution. It offers an intermediate step between the speed of DRAM and the stability of flash memory. Changing the polarization of ferroelectric domains is extremely fast, and the polarization remains stable without power for years, if not decades.

FeFETs, one of the most promising ferroelectric memories, are transistors in which the gate capacitor places a ferroelectric in series with a conventional dielectric, with or without an intervening metal layer (MFMIS vs. MFIS). The ferroelectric polarization acts as a permanent gate bias, either positive or negative, depending on the polarization state. This bias either raises or lowers the threshold voltage. The memory window is the difference between the V_tlo and V_thi values. Unfortunately, the memory window tends to move in the opposite direction from endurance, I_on/I_off ratio, switching speed, and other key metrics.

Managing the memory window
As previously reported, Xiaolin Wang and colleagues at the National University of Singapore showed that⁠[1] the memory window increases as the area ratio A_FE/A_MOS goes down. This can occur, for example, when the ferroelectric area decreases while the MOS area stays the same. However, in results presented at this year’s VLSI Technology Symposium, the same group observed that the footprint of the device depends on the MOS capacitor size, regardless of the dimensions of the ferroelectric layer.⁠[2] Reducing the ferroelectric area without scaling other dimensions is an inefficient use of silicon real estate. Instead, they proposed a three-dimensional device structure, in which ferroelectric hafnium zirconium oxide (HZO) makes up the bottom, planar layer, followed by tungsten fins coated with dielectric HfO₂.

These devices behave as metal/ferroelectric/metal/insulator/semiconductor (MFMIS) FeFETs, with 58% area reduction relative to equivalent planar structures. Building such a structure in reverse — with a planar dielectric and ferroelectric fins — is more complicated, though, because polarization and coercive field both depend on orientation.⁠[3]

Fig. 1: Memory window vs. area ratio in FeFET memories.

The thickness, film quality, and grain structure of the ferroelectric layer are important for overall device performance. At last year’s VLSI Technology Symposium, Zhouhang Jiang and colleagues at the Rochester Institute of Technology observed that charge trapping in the ferroelectric layer reduces the device read rate and endurance, while reducing the ferroelectric thickness appears to improve both. Unfortunately, a thinner ferroelectric layer reduces the difference between V_thi and V_tlo.

Instead, the RIT researchers proposed an asymmetric gate structure, with a conventional MOS “read” gate below the channel and a ferroelectric “write” gate above it. This device can bias the gate in opposite directions for read and write operations. The write operation “sees” the FE gate first. Increasing the ferroelectric thickness maximizes the memory window. The read operation, in contrast, sees the MOS gate first. When reading from the MOS gate, the memory window is modulated by a coefficient equal to the ratio of the FE gate capacitance to the MOS gate capacitance. With a thick MOS oxide, this value can be greater than one.⁠[4]

Even the device shape helps determine the switching speed. As Xiao Lyu and colleagues at Purdue University explained, switching begins when the applied field exceeds the coercive field (E_c) of the ferroelectric. “Switched” ferroelectric domains nucleate randomly, and domain walls propagate in all directions from those nuclei, like ripples in a pond. Long, narrow rectangular shapes switch more slowly than squares because the propagating domain walls need more time to reach the extreme ends of the features.⁠[5] The same work also identified the time needed for leakage current to propagate through the dielectric layer as a contributor to overall switching time.

In FeFET memories, as in ferroelectric transistors, the switch between polarization states in the ferroelectric causes an abrupt spike in the voltage delivered to the underlying MOSFET. These voltage spikes degrade the memory window and limit device endurance. In work at the University of Tokyo, Zuocheng Cai and others identified two different degradation mechanisms.⁠[6] High voltage cycling appears to generate permanent defects and traps, particularly at the metal/ferroelectric interface. Low voltage cycling, in contrast, can lead to incomplete switching, reducing the net polarization and therefore the memory window. This effect is especially notable in thin layers, where the polarization change is smaller to begin with. However, Cai observed, low voltage ferroelectric fatigue is reversible by applying a field strong enough to switch “stuck” domains.

Oxygen vacancies, good and bad
In previously reported work at TSMC, researchers specifically pointed to oxygen vacancies as contributing to leakage and ferroelectric breakdown.⁠[7] More recent studies give a more nuanced picture, though. Dong Zhang and colleagues at the National University of Singapore used solid phase epitaxy from polycrystalline HZO seeds to investigate the emergence of ferroelectricity in the material. Initially, deposited HZO crystallites have either monoclinic or tetragonal structure. Small grains tend to be tetragonal, as the tetragonal phase has lower surface energy, while large grains tend to be monoclinic.

The monoclinic phase is stable down to room temperature, and is not ferroelectric. The tetragonal phase, however, can transform to an orthorhombic, ferroelectric phase as it cools. Previous research found that oxygen vacancies at grain boundaries facilitate this transformation. When grains are smaller, there are more grain boundaries, and the ferroelectric phase is more likely to appear. In this group’s process, rapid thermal annealing at 400C for 60 seconds reduced the grain size of the HZO layer by about 30%, increasing remnant polarization by about 42%.⁠[8]

Fig. 2: Unit cells of monoclinic, ferroelectric, and tetragonal phases of hafnium oxide. Source: FMC

Oxygen vacancies also form at the TiN/HZO interface in TiN/HZO/TiN capacitors, and these also appear to facilitate the emergence of the orthorhombic phase.[9] Unfortunately, Yuejia Zhou and colleagues⁠ [10] at Peking University associated interface oxygen vacancies with excessive electric field density in the metal/ferroelectric interlayer. Not surprisingly, interface quality matters. Xiaolin Wang’s group found that ALD growth of their finned structure without breaking vacuum gave notably better results.

Looking to the ferroelectric future
For some time now, it has been clear that memory bandwidth and memory power consumption are serious concerns, especially for emerging machine learning workloads. The industry needs fast, non-volatile memories that are compatible with CMOS logic. Step by step, ferroelectrics researchers are working toward that goal.

References

1. X. Wang et al., “Deep insights into the Interplay of Polarization Switching, Charge Trapping, and Soft Breakdown in Metal-Ferroelectric-Metal-Insulator-Semiconductor Structure: Experiment and Modeling,” 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 13.3.1-13.3.4, doi: 10.1109/IEDM45625.2022.10019390.
2. X. Wang et al., “First Demonstration of BEOL-Compatible MFMIS Fe-FETs with 3D Multi-Fin Floating Gate: In-situ ALD-deposited MFM, LCH of 50 nm,> 2×109 Endurance, and 58.3% Area Saving,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185306.
3. S. -H. Kuk, et al., “Strategy for 3D Ferroelectric Transistor: Critical Surface Orientation Dependence of HfZrOx on Si,” VLSI Technology and Circuits, Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185431.
4. Z. Jiang et al., “Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window,” VLSI Technology and Circuits, Honolulu, HI, USA, 2022, pp. 395-396, doi: 10.1109/VLSITechnologyandCir46769.2022.9830172.
5. X. Lyu et al., “Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide,” VLSI Technology and Circuits, Honolulu, HI, USA, 2022, pp. 338-339, doi: 10.1109/VLSITechnologyandCir46769.2022.9830501.
6.  Z. Cai et. al., “HZO Scaling and Fatigue Recovery in FeFET with Low Voltage Operation: Evidence of Transition from Interface Degradation to Ferroelectric Fatigue,” VLSI Technology and Circuits, Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185295.
7.  J. H. Lee et al., “Investigation of Defect Engineering Toward Prolonged Endurance for HfZrO Based Ferroelectric Device,” IEDM, San Francisco, CA, USA, 2022, pp. 32.6.1-32.6.4, doi: 10.1109/IEDM45625.2022.10019519.
8. D. Zhang et al., “Grain Size Reduction of Ferroelectric HZO Enabled by a Novel Solid Phase Epitaxy (SPE) Approach: Working Principle, Experimental Demonstration, and Theoretical Understanding,” VLSI Technology and Circuits, Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185216.
9. T. Xin et al., “Atomic visualization of the emergence of orthorhombic phase in Hf0.5Zr0.5O2 ferroelectric film with in-situ rapid thermal annealing,” VLSI Technology and Circuits, Honolulu, HI, USA, 2022, pp. 343-344, doi: 10.1109/VLSITechnologyandCir46769.2022.9830185.
10. Y. Zhou et al., “Ferroelectric and Interlayer Co-optimization with In-depth Analysis for High Endurance FeFET,” IEDM, San Francisco, CA, USA, 2022, pp. 6.2.1-6.2.4, doi: 10.1109/IEDM45625.2022.10019465.

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