Ferroelectric Memories: The Middle Ground

The first article in this series considered the use of ferroelectrics to improve subthreshold swing behavior in logic transistors. The prospects for ferroelectrics in logic applications are uncertain, but ferroelectric memories have clear advantages.

The two most common commercial memories lie at opposite ends of a spectrum. DRAM is fast, but requires constant power to maintain its information. Flash memory is non-volatile, stable enough for long term bulk storage, but not particularly fast. Ferroelectric memories fall somewhere between the two, and potentially can provide a necessary intermediate step.

Changing the polarization of ferroelectric domains is extremely fast, and the polarization remains stable without power for years, if not decades. As system designers seek to manipulate ever-larger data sets, while reducing power consumption, ferroelectric memory may be part of the solution.

But which ferroelectric memory isn’t clear. The term actually encompasses at least three different technologies. All of them depend on the polarization behavior of ferroelectric materials, but they exploit those materials in different ways. While they are structurally similar, they depend on different physics and have different material requirements. A ferroelectric that is ideal for one design may be exactly wrong for the others.

FeRAM
The simplest ferroelectric memory design, FeRAM, integrates a metal/ferroelectric/metal capacitor into a BEOL process, placing a conventional MOSFET underneath each cell. To store data, an electric field switches the capacitor between the P- and P+ polarization states. Unfortunately, reading the polarization value is a destructive operation, after which the cell must be rewritten, as Shan Deng and colleagues at the Rochester Institute of Technology explained in work presented at the 2021 GLSVLSI conference[1]. Commercial FeRAM applications therefore require unusually high endurance, above 10⁴ cycles.

Memories based on zirconium-doped HfO₂ capacitors are attractive because they are compatible with existing CMOS manufacturing processes, but design integration remains challenging. For logic compatibility, designers would like to reduce the write voltage below 1.5V. Reliable write operations, however, require an electric field two or three times larger than the coercive field (E_c) needed to change the ferroelectric polarization.

Deng explained that the ideal FeRAM material would have an E_c of about 0.5 MV/cm. Hafnium oxides have coercive fields between 1 to 1.5 MV/cm, and therefore require higher write voltages. At the same time, the FeRAM sense margin is proportional to the remnant polarization in the material. Materials with high remnant polarization and low E_c are not yet available.

The high fields needed for ferroelectric switching also affect the long-term reliability of the device. During deposition, an interfacial layer — believed to be a metallic oxide — forms between the ferroelectric and the metal capacitor plates. It seems to passivate both materials and facilitate bonding at the interface. Both the switching field and the ferroelectric dipole itself can degrade this interfacial layer, affecting both polarization retention and cycling endurance, according to Ruben Alcala and colleagues at TU Dresden, in work presented at December’s IEEE Electron Device Meeting[2]. The sense margin deteriorates as the remnant polarization decreases with repeated cycling. Over time, charged oxygen vacancies establish an internal electric field in the ferroelectric material. This field “imprints” the memory so that one polarization state is preferred. To overcome imprinting, the peak field needed for successful switching increases.

Ferroelectric tunnel junctions
A second type of ferroelectric memory, ferroelectric tunnel junctions, uses polarization to modulate the junction’s tunneling barrier and therefore its resistance. Reducing the thickness of the ferroelectric layer increases the tunneling probability, but also reduces the on/off current ratio, according to Deng. Increasing the polarization charge helps, increasing the on current and improving the on/off ratio.

In FeRAMs, the presence of a depolarization field is undesirable, reducing retention time. In FTJs, though, a depolarization field is necessary to make sure that the “on” and “off” states have different barrier heights.

FeFET memory
The third approach to ferroelectric memory is based on ferroelectric transistors (FeFETs). FeFETs place a ferroelectric in series with a conventional dielectric, with or without an intervening metal layer. The threshold voltage depends on the polarization state of the ferroelectric. The memory window is the difference between the V_tlo and V_thi values.

Researchers have demonstrated two possible device structures — metal/ferroelectric/metal/insulator/semiconductor (MFMIS) and metal/ferroelectric/insulator/semiconductor (MFIS). In both cases, the area ratio A_FE/A_MOS is a critical parameter, according to Xiaolin Wang and colleagues at the National University of Singapore reported at IEDM [3]. As this ratio goes down — for instance if the ferroelectric area decreases while the MOS area stays the same — the memory window increases.

Fig. 1: Memory window vs. area ratio in FeFET memories. Source: University of Singapore/IEDM

Structurally, FeFET memories are similar to ferroelectric logic transistors. In both applications, the switch between polarization states in the ferroelectric causes an abrupt spike in the voltage delivered to the underlying MOSFET. FeFET logic devices depend on this “negative capacitance” transient to achieve a steep subthreshold swing, and often are described as NCFETs for this reason.

Unfortunately, the voltage spikes associated with ferroelectric switching also can induce defects and charge trapping. In FeRAMs, as discussed above, a high remnant polarization is desirable because it increases the sense margin. In FeFET memories, though, incomplete switching leads to variability in the device threshold voltage, requiring a larger pulse to ensure a successful write. Reducing the remnant polarization in FeFET memories reduces stress, according to Deng.

As potential markets for commercial FeFET memories emerge, researchers need to analyze trapping, defect generation, and device reliability in more detail. According to Puyang Cai and colleagues at Peking University, [4] the two dominant degradation mechanisms appear to be related to an increase in V_tlo. On one hand, increasing V_tlo reduces the difference between V_tlo and V_thi, and therefore the memory window. Increasing V_tlo also introduces a “read after write” delay — defined as the delay after a successful write before the memory value can be read — because the on-state resistance increases.

Puyang Cai’s group identified two different potential trapping mechanisms. Type A traps, which appear in the interfacial layer near the channel, increase at first then stabilize. They appear to be responsible for read after write delay. Type B traps, within the HZO layer, appear to increase continually and are associated with memory window degradation. A second Peking University group, in work reported by Yuejia Zhou and colleagues [5], showed that electric field density in the metal/ferroelectric interlayer plays a critical role in defect generation. A high interlayer field appears to generate traps in the ferroelectric. Researchers at TSMC specifically pointed to oxygen vacancies in the ferroelectric as contributing to leakage and ferroelectric breakdown [6]. In their work, optimizing ferroelectric deposition conditions reduced roughness and led to more consistent interlayer composition. To reduce the interlayer field, Yuejia Zhou’s group proposed aluminum, rather than zirconium doping. HAO appears to have a lower barrier to polarization than HZO, and therefore a lower coercive field.

Overall, the future of ferroelectric memories looks bright. Though endurance and reliability need to improve, the issues seem related to process and design optimization rather than the fundamental physics of the material.

The last installment in this series will look still further ahead, at applications linking ferroelectrics with 2D semiconductors.

References
1. S. Deng, et. al., “Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization.” In Great Lakes Symposium on VLSI 2021 (GLSVLSI ’21), June 22-25, 2021, Virtual Event, USA. ACM, New York, NY, USA, https://doi.org/10.1145/3453688.3461743
2. R. Alcala et. al., “The Role of Interface Dynamics on the Reliability Performance of BEOL Integrated Ferroelectric HfO2 Capacitors,” IEDM 2022, paper 32.8.
3. Xiaolin Wang, et. al., “Deep insights into the Interplay of Polarization Switching, Charge Trapping, and Soft Breakdown in Metal-Ferroelectric-Metal-Insulator Semiconductor Structure: Experiment and Modeling,” IEDM 2022 paper 13.3.
4. Puyang Cai, et. al. “Deep Understanding of Reliability in Hf-based FeFET during Bipolar Pulse Cycling: Trap Profiling for Read-After-Write Delay and Memory Window Degradation,” IEDM 2022 paper 32.2.
5. Yuejia Zhou, et. al., “Ferroelectric and Interlayer Co-optimization with In-depth Analysis for High Endurance FeFET,” IEDM 2022, paper 6.2.
6. J. H. Lee, et. al., “Investigation of Defect Engineering Toward Prolonged Endurance for HfZrO Based Ferroelectric Device,” IEDM 2022 paper 32.6.