Has 3D NAND Fallen Flat?

Rollout is pushed to 2016 or 2017 back because it’s harder to manufacture than initial projections.

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Today’s planar NAND technology will hit the wall at 10nm, prompting the need for the next big thing in flash memory—3D NAND. In fact, 3D NAND may extend NAND flash memory for the next several years and enable new applications. And it will also drive a new wave of fabs and tool orders.

But the transition won’t be as smooth as previous rollouts. 3D NAND is harder to manufacture than previously thought, causing vendors to delay or push out their volume production ramps. Now, 3D NAND is expected to move into mainstream production in 2016 or 2017, which is a year or two later than expected. There’s good reason, too: 3D NAND is a complex device that resembles a skyscraper, in which horizontal levels are stacked and then connected using tiny vertical channels.

Analysts agree that the 3D NAND ramp will take longer than expected, but experts differ regarding the issues with the technology. “You should see client solid-state drives based on 3D NAND shortly,” said Greg Wong, an analyst with Forward Insights. “So it’s happening. But it will take longer to ramp because the suppliers, other than Samsung, are so far behind. You need multiple suppliers to make it mainstream and that won’t happen until 2016 at the earliest.”

Others believe the ramp could take even longer. “We believe broader mass market adoption (for 3D NAND) is beyond 2017, which is later than the 2015/2016 time frame most seem to be expecting,” said Doug Freedman, an analyst with RBC Capital Markets. “There is a steep learning curve associated with the ramp of 3D due to the many technical challenges, (such as) multi-stack patterning, metrology, defect monitoring and cell optimization. (This) could lead to lower than expected initial output as yields and data retention capabilities are challenged.”

So, after years of R&D and hype, has the 3D NAND market fallen flat? Eventually, 3D NAND will happen, but the migration from planar to 3D NAND will be a long and difficult process. And at least now the important questions are clear: What’s holding up the 3D NAND market? And what are the fabrication challenges and solutions to speed up the ramp?

Planar vs. 3D
Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. But at that node, vendors are struggling to scale the critical element in a NAND device—the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.

Realizing that planar NAND is on its last legs, Samsung last year got a jump on its rivals and introduced the industry’s first 3D NAND device. Samsung’s V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.

Others have different strategies. For example, the SanDisk/Toshiba duo will extend planar NAND for one more generation in the 1xnm regime. Then, SanDisk/Toshiba will debut 3D NAND in 2016, when the technology is price competitive with planar NAND. “The challenge is cost,” said Ritu Shrivastava, vice president of technology at SanDisk. “The initial generations of 3D NAND will not be cost competitive with planar NAND.”

Another vendor, Micron Technology, is shipping 16nm planar NAND, which represents its last 2D technology. Then, Micron will move to 3D NAND. “10nm may be the fundamental limit (for planar NAND),” said Mark Durcan, chief executive of Micron. “So, we are all headed towards 3D in the future. But planar NAND will still be around for a long time. There are still a lot of applications that use 2D NAND.”

Still, Micron and SK Hynix have pushed out their initial 3D NAND sampling dates from the first half to the second half of 2014, according to Pacific Crest Securities. “3D NAND is currently more expensive than planar NAND,” said Monika Garg, an analyst with Pacific Crest. “3D NAND MLC has endurance as high as SLC planar NAND, which makes it highly suitable for enterprise SSD applications. But enterprise SSDs consume less than 5% of total NAND bits.”

Like baking a cake
On the technology front, meanwhile, there are some major differences between planar and 3D NAND. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.

Planar NAND requires advanced lithography, while 3D NAND does not. “(In 3D NAND, chipmakers) are basically shifting the scaling challenges from lithography to deposition and etch,” said Terrance Lee, vice president of marketing and strategy at Applied Materials.

On the other hand, 3D NAND introduces several new manufacturing techniques, which adds complexity and possible problems in the flow. “As for manufacturing challenges, 3D NAND is the first-ever semiconductor to use the following technologies—thin-film transistor NAND strings; over ten poly-oxide layers; stair-step etching; charge-trap NAND strings; and the ‘macaroni channel,’ ” said Jim Handy, an analyst with Objective Analysis.

One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung’s V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung’s 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.

The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow—alternating stack deposition.

Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers. “(3D NAND) is actually 20% higher in terms of layer-to-layer control than 2D,” Applied’s Lee said. “Nano defect control is also important. A small particle in the bottom of the stack becomes a killer defect.”

To address the challenges, Applied Materials and Lam Research have recently rolled out a new class of CVD tools, which enables alternating stack deposition with precise control and low defectivity. “Previous-generation (CVD) products, whether it’s ours or our competitors, will have a hard time doing this with angstrom-level control,” Lee said.

Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.

Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. “They are 40:1 now,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “We are being asked to do 60:1 and higher. Essentially, whatever we can do, the device makers will take. That means they can add more layers.”

The other challenge is to etch over a million tiny trenches, or channels, in a device, which must be parallel and uniform. “If you have a hole that isn’t straight, you get a different performance on the ones at the top versus the ones on the bottom,” Hemker said.

Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a “macaroni channel,” according to Objective Analysis.

Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.

Unlike other 3D NAND devices, Samsung uses a gate-last process. The tower structure is coated with a silicon dioxide tunnel dielectric layer. This is followed by a silicon nitride charge trap and an alumina high-k gate dielectric, according to Objective Analysis. Finally, the remaining gaps in the finned pillar are filled with a tantalum nitride control gate material, creating a vertical NAND string of TANOS transistors.

Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step—staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.

Ideally, 3D NAND vendors would prefer to pattern the entire staircase with one lithography step. “Today, it takes three litho steps to form a 24-layer stair-step,” Objective Analysis’ Handy said. “That’s one per eight layers. The industry hopes that 3D NAND will last through 128 or more layers. At (128 layers), it would require 16 critical mask steps for the stair-step alone. It would be hard to economically manufacture a wafer if it went through this many litho steps.”

Process control and test
At various steps, the structure must also go through a rigorous metrology and inspection flow. One of the many challenges is to find a defect in a multi-layer 3D NAND stack and determine its exact location. “My tool has found a defect, but where is it? Sometimes, we don’t have the intelligence to know if it came from the fifth layer or not,” said Brian Trafas, chief marketing officer at KLA-Tencor. “It might be at the fifth layer. I may need to take the device to a failure analysis lab and do a cross section with a TEM. You can do that in R&D, but not in production.”

To address the issues, KLA-Tencor is boosting the capabilities of its tools. For example, using a broadband plasma illumination source, KLA-Tencor’s latest patterned wafer defect inspection platform delivers twice the light of its predecessor, enabling the use of DUV wavelengths. The tool can also determine the best optical settings for defect detection, thereby reducing process control times.

“We have made modifications to our illumination system to have available wavelengths that can penetrate deeper into these stacks,” Trafas said. “We have a version that has UV wavelengths. We’ve also extended the broadband spectrum on our optical CD tools.”

Not to be outdone, the chips must also be tested. 3D NAND can be tested using today’s ATE, but the test times will go up. “There are longer test times,” said Skanda Visvanathan, vice president of memory test sales at Advantest. “But in general, for testing, we don’t expect that much of a difference. We can run a standard test.”

Another ATE vendor agreed. “There are more levels to control and more levels to test. All of that is built into the tester now. The test times go up, because there are more bits per array,” said Tim Moriarty, vice president and general manager at Teradyne. “Then, when you get into multi-die, it’s all tested through the controller. So there are more test times, but we also do more parallelism. So the cost-of-test actually goes down with the systems we have in place.”