HBM, Nanosheet FETs Drive X-ray Fab Use

Paul Ryan, vice president and general manager of Bruker’s X-ray Business, sat down with Semiconductor Engineering to discuss the movement of x-ray metrology into manufacturing to better control nanosheet film stacks and solder bump quality.

SE: Where are you seeing the greatest growth right now, and what are the critical drivers for your technology from the application side?

Ryan: One big growth area that has been taking off is automotive, and that really is on the safety-critical side. A lot of these defects don’t necessarily kill the device straightaway. If they do, they are caught at electrical test. It’s detecting defects that impact performance further down the line that are critical. One of the key applications we’re pulling through now is alignment of the dies (in high-bandwidth memory), where you’ve got maybe eight stacks on top of each other and looking at how they’re aligned and measuring online thickness. That’s a real emerging area for us. For HBM, we’re working with companies on the through-silicon vias and redistribution layers (RDLs). The biggest things we measure with XRF are thickness and the composition of alloys. Measuring solder composition, we look at things like RDL and UBM metal film thickness — silver content in bumps, for instance — and looking for voids or bridging defects within 3D packaging. Consistency is the key thing, making sure the RDL has the right alloy composition.

SE: One of the problems in the past was that X-ray inspection was too slow, so it was limited to spot inspection. Has that changed?

Ryan: Yes, that is certainly changing. We’re always innovating the design of X-ray sources, squeezing more power out, more photons out, and optimizing the design of the optics. We’ve recently upgraded our detection chain, which is significantly improved. Our latest X-ray fluorescence (XRF) product for the front-end-of-line significantly improves throughput to reach 30, 40, 50 wafers an hour, which is really production-worthy.

SE: Are there other hot applications?

Ryan: X-ray diffraction is measuring the level of defectivity in SiC wafers for various GaN power applications, because the SiC defectivity can vary quite dramatically wafer-to-wafer and from batch-to-batch. So customers really look at the quality of the wafer, both from a ‘do we use it’ perspective, but also to optimize the device size and substrate used, for instance. Some of the more expensive, bigger devices need a lot more real estate from the wafer. So you can start optimizing which devices to put onto which wafers.

SE: What kind of defects are you finding?

Ryan: The biggest killers are things like micro-pipes, or essentially a pipe straight through the wafer, which basically kills it. But then there’s a lot of threading dislocations that can be critical. And then what are called basal-plane defects, which are essentially threading dislocations on their basal plane crystal side. They range in size from atomic level to micron-sized dislocations.

SE: To what extent do your systems use machine learning (ML) or AI?

Ryan: It depends a bit on the technique. On the metrology side, we tend to do much more simulation, analysis and regression, and that’s still the best approach. But as we move much, much faster with inspection techniques, then for sure we use machine learning.

SE: In the past, X-ray tools have been beyond the price capability for OSATs. Has that changed?

Ryan: There are two different markets. We don’t have OSATs buying, but we’re seeing a lot of activity in Taiwan for both high bandwidth memory and the logic side by the tier-one companies. Over time, I would expect them to push it down the chain. But right now, tier-ones have taken a lot of this in-house, and it is customers you wouldn’t expect to do be doing this in-house.

SE: What about the transition to going bump-less? You almost need to be able to see inside, right?

Ryan: Traditionally, the inspection has always been on the packages, almost at a PCB level. And certainly more and more, we’re moving further up the chain. So, we do X-ray inspection on strips after singulation. But we are now moving again, more toward pre-dies, looking at on-wafer, which has a much higher value when you catch things much earlier in the process. That’s a fairly recent change.

SE: On the transistor side, as the industry move down from finFETs to forksheet FETs, and perhaps carbon nanotube FETs. Will chipmakers be doing more in-depth inspection?

Ryan: It’s going to depend on how it’s implemented. Once you get down to the carbon nanotube work, you could envisage what the crystal structure looks like. And when you go to these materials and how they are constructed, the phase of those is pretty important.

SE: What’s the limit in terms of how far you can go in terms of resolution? Do other technologies compete in this realm?

Ryan: We can push towards can just below 1µm. Some of the others, like X-ray CT (computed tomography), has a much better resolution but a very small field of view. So, they’re okay for failure analysis, but they are just too slow for production. On the packaging side, we’re down in 3µm resolution, which for back-end defects is fine. On the wafer, we’re imaging the impact of defects on the lattice. That strain field is much, much bigger than the defects themselves. So you’ve got strain that has got to be able to propagate.

SE: How has X-ray tooling changed with production use?

Ryan: Previous X-ray diffraction systems were very much a Swiss army knife, and any time you have a Swiss army like tool, you’ve compromised everything. There’s been a lot of work, both by Bruker and our customers, slimming down what the tool needs to do and optimizing it for what they’re trying to monitor. By doing that, you increase the throughput, increase productivity, and you improve the cost of ownership.

SE: So X-ray is finally coming into its own? It’s taken a while.

Ryan: Yes, it certainly is taking off now. We’re in proper production.

— Ed Sperling contributed to this report.