High-NA Lithography Starting To Take Shape

The future of semiconductor technology is often viewed through the lenses of photolithography equipment, which continues to offer better resolution for future process nodes despite an almost perpetual barrage of highly challenging technological issues.

For years, lithography was viewed as the primary manufacturing-related gating factor to continued device scaling, beset by multiple delays that affected throughput in the fab that persisted all the way to the 7nm process node. Those issues have since been overcome, but a host of new ones are on the horizon, as well as some important improvements.

Industry experts from the design, photolithography, test and measurement, and packaging communities gathered at this year’s SEMICON West and DAC to discuss product roadmaps for extreme ultraviolet (EUV) and the forthcoming high-numerical-aperture EUV (high-NA EUV), including the latest research and development efforts, as well as barriers to advancing lithography innovation and scaling density. Areas of discussion included improving efficiencies in power and process, enhancing metrology techniques, and exploring novel solutions such as curvilinear masking and new chemistries for photoresists. Amid these advances, however, lies a consistent focus on achieving higher yields, higher throughput, and lower cost per chip.

High-NA EUV
Much of this year’s discussion centered on what comes next for EUV and the timeline and technology requirements for high-NA EUV. Michael Lercel, senior director of strategic marketing at ASML, said the goal is to improve energy efficiency for EUV, as well as the development status of their next generation high-NA EUV tools.

“EUV tools are not the most energy efficient, but we’re doing whatever we can to improve the energy efficiency and the tool itself, such that the energy it takes to make each wafer is significantly improved,” Lercel said, highlighting the role of numerical aperture (NA) in the evolution of these tools. While the overall energy usage per exposure is much higher than 193i lithography, the ability to support single patterning of higher density devices means fewer exposures are necessary. That, in turn, reduces overall energy output and cycle time.

High-NA increases the numerical aperture from 0.33 to 0.55, improving the resolution from about 26 to 30 nanometer pitch to 16 nm pitch. By increasing the numerical aperture, the resolution improves, but the optics have to get larger. That necessitates a larger machine, which comes with an added benefit. The larger tool is designed for better serviceability to maintain high productivity levels and improve the recovery time back to manufacturing after servicing. The new high-NA systems are also more modular, making it easier for the service team to replace individual modules.

Lercel revealed that the first fully assembled system has been built, but is not operational yet as it does not have the final optics. He expects first light on these systems later this year.

“We see the 0.55 insertion coming up in the next few years, and anticipate customers will start to put those in production by 2025,” he said (see figure 1). “After that, we are exploring hyper-NA with a 0.75 numerical aperture, which we see coming in about a decade.

Fig. 1: ASML expects 0.55 to be in production within four years, and 0.75 Hyper EUV in about a decade. Source: ASML/SEMICON West

E-beam metrology
Using a higher NA for exposure means that the light hits the wafer at a smaller angle, known as the incident angle. As a result, the vertical structures or “aspect ratios” of the features on the wafer become more challenging to observe and measure accurately. Ofer Adan, senior director at Applied Materials discussed the need for more advanced metrology tools to support high-NA processes. At the 2nm node and beyond, defects become more difficult to detect with the imaging capabilities of conventional electron beam technology.

Adan pointed to recent developments in cold field emission (CFE) technology as one possible solution for metrology needs for high-NA. CFE is a type of e-beam source that operates at lower temperatures and offers several advantages over traditional thermionic sources, including improved spatial resolution, better beam stability, and reduced spherical aberration. CFE operates at room temperature, resulting in narrower, higher-energy electron beams that produce higher resolution and faster imaging speed compared with conventional thermal field emission (TFE) technology (see figure 2). This technology’s higher brightness helps provide higher-resolution imaging and measurement, but the smaller spot size means throughput is significantly impacted.

“There is a thermal field curve with CFE, which is the tradeoff between the imaging speed and the resolution,” said Adan. “You can reduce the resolution and get faster throughput, or you can keep the same speed and get higher resolution. CFE offers a 10X faster speed than TFE.”

Fig. 2: CFE offers 10X faster imaging at the same resolution as TFE. Source: Applied Materials/SEMICON West.

Until recently, use of CFE has been limited to lab environments because the stability of the e-beam column was insufficient for the stringent requirements of high-volume semiconductor manufacturing. Adan mentioned two innovations that have solved the stability challenge. One, an extreme ultra-high vacuum inside the column, and the second is a cyclical self-cleaning process that continuously removes contaminants from the CFE source, enabling stable and repeatable performance.

New process technologies for high-NA
Angélique Raley, director in TEL’s etch business unit, pointed to two significant trends shaping the future of EUV. The first is the shift from 2D to 3D structures, specifically the transition from finFET to gate-all-around (GAA) devices, which significantly impacts the processes required in chip fabrication. The second revolves around the continuous critical scaling of EUV, especially as it relates to the reduction of metal pitch to as low as 12 nm.

“As we move from GAA to stack channel FETs (CFETs), we face even higher aspect ratio requirements,” said Raley. “This development again stresses the importance of highly controllable isotropic and directional etching processes.”

Gate-all-around (GAA) devices will be defined by epitaxial (epi) deposition involving multiple layers, demanding impeccable control of this deposition process. Semiconductor manufacturers will need to devise highly controlled isotropic etches that can etch materials simultaneously in all directions with selectivity.

Plasma etching will remain indispensable, particularly for high-aspect-ratio etches. For example, contact etching is an intricate oxide etching process that demands a high degree of control.

With the introduction of high-NA EUV, manufacturers will have to decide whether to use a chemically amplified resist or a metal-oxide-based resist. This transition, coupled with a reduced depth of focus, will necessitate thinner resist and therefore highly precise process control for etching. Thinner resist also means more extensive use of hard masks, because the photoresist itself erodes more quickly in etch chemistries.

Dry resist
One solution to the resist issue with high-NA is dry resist. Compared with the conventional chemically amplified (CAR) photoresist process, dry resist uses a gas precursor process, involving dry resist material and a dry develop process, said Benjamin Eynon, senior director of EUV dry resist marketing at Lam Research. Its molecular size is six times smaller than CAR, allowing for much finer details to be printed (see figure 3). It also simplifies the process by eliminating liquid, reducing the potential for pattern collapse. Eynon noted that dry resist also offers a 5X to 10X reduction in waste, making it a greener choice.

Fig. 3: Dry photoresist imaging can pattern 16nm and 13nm lines and spaces with 3nm of line-width roughness. Source: Lam Research/SEMICON West

“Dry resist produces more consistent and predictable structures with less waste,” said Eynon. “We also have a resolution advantage for high-NA, where CAR is struggling below 35nm pitch, and we’re seeing better results far below that.”

He explained that making changes to resist thickness is much simpler with dry resist than with traditional CAR. “In the past, if I had to ask the resist supplier for a resist that spins thinner, I would have to wait six months for all the testing. Now we can just change the recipe and lay it down.”

Dry resist offers advantages in terms of the processing window and defectivity, which is negligible, but there are still barriers to overcome. Lowering dose for high-NA can lead to increased roughness, so more work needs to be done to balance dose reduction with other factors such as line-width roughness (LWR).

Steven Scheer, senior vice president of advanced patterning, process, and materials at imec, also highlighted the advantages of metal oxide resist over the limitations of CAR for line and space imaging at the smaller pitches offered by high-NA. But he added that further research is required to reduce the dose and improve defectivity. Lower dose on EUV scanners correlates with higher throughput.

Imec and ASML currently are constructing a high-NA pilot line in Veldhoven, Netherlands, on ASML’s campus. That is due to open in the first half of 2024 to cooperatively research, test, and develop the tools and processes for high-NA EUV lithography.

“High-NA EUV is more of an evolution rather than a revolution,” said Scheer. “We have to compress the timescale to produce these new technologies in roughly two years.” Scheer anticipates the ideal insertion point for high-NA will be the 14 angstrom (1.4 nm) node.

Another challenge with high-NA EUV involves metrology, particularly in regard to imaging of very thin materials. Scheer cited difficulties with measuring weak signal return in CD SEMs. Optimizing landing energy, different materials, and machine learning algorithms for de-noising, contrast extraction, or automatic defect classification were suggested as potential solutions.

Mask innovation is another key area that Scheer sees as an evolutionary process for high-NA EUV.

“In terms of masks and imaging, one of the key things that’s important is that we explore low-n masks in order to improve the overall contrast,” said Scheer. “When you start to get to 24 nanometer pitch or below, you start to lose contrast unless you’ve actually implemented the low-n masks. So we think this is an important technology that needs to be developed.”

Curvilinear masks for curvy design
For three decades, semiconductor mask technology remained largely unchanged, with mask creation carried out on variable shaping machines that restricted variable elements to a 45-degree angle. As features shrank and became more complex, e-beam and multibeam mask writers offered flexibility in design. Now, virtually 100% of masks are crafted using multibeam technology, introducing new opportunities for more intricate and efficient designs on high-NA systems.

In a panel presentation at DAC, Aki Fujimura, CEO of D2S, discussed the emergence of curvilinear manufacturing that is possible now and gaining interest for its potential to increase yield, reduce chip size, use less power, and improve performance and reliability.

“Any shape can now be projected with the same accuracy in the same amount of time,” said Fujimura. “Mask write times no longer are a function of what kind of shape you’re trying to present, and therefore the mask cost is constant, regardless of the shape that you’re projecting.”

A key objective of high-NA EUV is to reduce complexity and reduce the overall turnaround time and cost of wafer manufacturing, and curvilinear masks promise significant improvement in those areas.

Steve Teig, CEO of Perceive, demonstrated how curvy design can reduce the number of vias in a chip design by up to 50%, reduce wiring by 30%, and reduce costs of manufacturing by up to 30% (see figure 4). “Reducing the number of vias can reduce wire length a lot more than you think,” he said. “It is possible to reduce the number of vias enormously and make chips much smaller, much faster, much less expensive, and with many fewer layers. This is the promise of curvy routing.”

Fig. 4: Perceive’s Teig explains why vias are not your friend, at the Curvy Design Panel, DAC 2023. Source: Semiconductor Engineering / Susan Rambo

Curvilinear designs also resolve many stochastic issues at lower nodes. Teig compared current lithography processes to shooting a bow and arrow at a target and aiming for the outside edge rather than the bull’s-eye. “If you’re printing a sausage-shaped wire instead of a square one, you can aim for the center, and the stochastics and line-edge roughness issues become far less problematic,” he said.

Variation poses another challenge. “Ninety-degree corners are impossible to actually produce on a wafer,” added Fujimura. “We know this, but that is the design we have, so we try to get as close as possible. And the most important thing in manufacturing is variation — not just that you want to get this right, on the average, but that you want to get the standard deviation of the average to be as small as possible.”

John Kibarian, president and CEO of PDF Solutions, highlighted that curvilinear design promises an innovative future, especially in the realm of integration, from system design to atom rearrangement. Its unique benefits, such as reducing track height while maintaining porosity and stability, are crucial for future scaling.

Yet, the shift towards curvilinear manufacturing is not without its challenges. The widespread adoption of this innovative design approach necessitates significant changes in electronic design automation (EDA) software, organizational dynamics, and testing and measurement protocols. However, these obstacles are far outweighed by the promise of increased yield, reduced chip size, decreased power consumption, and enhanced performance and reliability that curvilinear design offers to semiconductor manufacturing.

“The future is going to be a lot more about innovation as integrators,” said Kibarian. “If you look at what our industry is saying the next decade is going to entail, it’s about integration up and down the stack from system design, to lithography, to metrology, to new materials that enable process improvements. Anything that lets you reduce size, reduce power, and reduce costs while maintaining stability will find its way into the process, and that’s one of the biggest potential benefits for curvy design.”

Conclusion
The evolution of photolithography is a cornerstone for semiconductor scaling, enabling the continuing miniaturization of circuit patterns and the corresponding increase in circuit density and performance. The future of lithography looks promising with the introduction of more energy-efficient EUV tools, the evolution of high-numerical aperture tools, and the holistically integrated approach to innovations for improving resolution and controlling dimensions.

While today’s industry has managed to achieve some success in integrating new materials into the ecosystem, the reduction in field size offered by high-NA devices presents new challenges for resists, metrology, mask making, and process control. If the past 40 years have proven anything, though, it’s that the industry always finds a way forward.

Related
High-NA EUV Progress And Problems
Why it’s necessary, when it’s coming, and what still needs to be done.
Assist Layers: The Unsung Heroes Of EUV Lithography
Various materials work in concert with the scanner, photoresist and photomasks to make EUV lithography work.