Chiplet-based products must accommodate small differences in die size and bump pitch, placing new demands on manufacturing tools.
Multi-die assemblies are becoming more common and more complex due to technology advancements and market demands, but differing die dimensions are making this process increasingly challenging.
To fully enable a multi-chiplet ecosystem, standardized component handling and interfaces are needed. The underlying concept is similar to LEGO blocks that simply snap together, yet it’s nowhere near that simple. Building these multi-die assemblies today involves various flavors of interposers, bonding methods, and packaging approaches. Also different die dimensions (e.g., x, y, z) require a wider assembly process envelope. And as the number of chiplets on interposers and/or substrates increases, managing warpage, thermal dissipation, and mechanical stability become proportionately more difficult.
This is made even more challenging when those dies/chiplets are sourced from different foundries. Dies may be manufactured with different heights, areas, and bump pitches. While not insurmountable, those inconsistencies increase the time, effort, and cost needed to make these systems work.
Fig. 1: Multiple die entering the assembly process flow, exiting as a chiplet-based system. Source: A. Meixner/Semiconductor Engineering
Addressing these inconsistencies requires new materials and new process recipes, which often increase the number of manufacturing steps. That also may require new equipment. Add up all the various pieces and processes, and the cost is too high for many applications.
Fig. 2: High-level overview of assembly process. Source: A. Meixner/Semiconductor Engineering
“Multi-die assemblies in some shape or form have always been with us for decades, going by the names of multi-chip modules or system in package,” said Marc Swinnen, director of product marketing for semiconductor products at Ansys. “But now the assembly technology has improved. We have finer resolution bumped technology – C4 bumps, microbumps, and bumpless (hybrid bonding). So it’s now possible to put hundreds of thousands of connections per square centimeter. This was not quite feasible before, and even now it’s difficult. Secondly, because the systems have gotten so big, there’s a need for it. And you can get bigger beyond a reticle size with better yield numbers.”
One of the big benefits of multi-chiplet systems is the ability to mix and match processes. For example, an analog die may be developed at 90nm while an advanced logic chiplet may be developed at 5nm. But this creates a mismatch in physical dimensions and bump densities.
“Silicon die with different bump diameters and pitches are becoming quite common, especially for chiplet-based constructions,” said Mike Kelly, vice president of chiplets and FCBGA integration at Amkor. “The die-to-die interfaces, like UCIe, can allow small pitches. The rest of the device, including power, memory interfaces and miscellaneous I/O don’t normally need these fine pitches.”
Another advantage of heterogeneous integration is the flexibility it enables. Chiplets can be swapped out without having to redesign the entire system. However, what appears straightforward in theory can result in a more complex assembly process.
“In general, the vision of being able to mix-and-match chiplets sounds easy and it sounds very attractive,” said Lesley Polka, principal engineer in foundry technology development at Intel. “But the manufacturing reality turns into a lot of details that need to be worked out, especially when you’re sourcing chiplets and packaging components from many different players. They need to be on the same page down to design and manufacturing details. And really, the only way to do that is to get standards going in the industry for everything from the manufacturing piece of it to the design tools themselves. For manufacturing that means interconnects, bump pattern, metallurgies, etc., so we can easily make things mix-and-match.”
Accommodating differing lateral dimensions
Differences in bump density and die dimensions make die attachment across a large substrate more challenging for multiple steps. Add in the shifts from C4 to thermo-compression bonding, and eventually to hybrid bonding, the tolerances for misalignment plummet. Increase the number of dies from 3 to 10 to 50, and there’s a complex set of process interactions for engineering teams to decipher while balancing yield, cost, and reliability. With x and y differences, they need to consider everything from handling to bonding recipes.
Today, there are a wide range of die areas, some with an order of magnitude difference. Similarly, the breadth of bump density is projected to become even wider.
“We’re going very quickly from standard 100-micron bump ranges to pitches lower by at least one factor, and you need to be able to deal with that range on a single package,” Intel’s Polka noted. “As a hypothetical example you could have a range from 1 to 100 or even 200 microns on the same package. You’re dealing not only with the density scaling piece, but a wide process envelope at the same time.”
Fig. 3: Illustration of different die dimensions x and y. Source: A. Meixner/Semiconductor Engineering
Die differences in the x-y directions can affect process recipes, tooling, manufacturing efficiencies, and more. The physical handling of components (i.e. diced wafer to substrates) seems a mundane task, but each component having unique dimensions may require different handling within the same tool or multiple tools. This increases costs.
“It could be die size. It could be die height. It could be how you actually dice the die in terms of scribe widths, etc. It can even come down to the definition of what the physical size of the die is at the end of a processing step,” said Polka. “But it also matters how we deliver die to substrate suppliers, i.e., the carrier for delivery.” For example, to facilitate die with various x-y dimensions the industry would benefit from a standard carrier size that would have flexibility to deal with different die sizes.
Initial placement of chiplets on to the substrate impacts the bonding process. Finer bump pitch demands higher placement accuracy in both the x, y and rotation (theta). Thus, substrates that need to support multiple bump pitches require pick-and-place equipment to meet smaller pitch accuracy. And with larger die, you need to watch the corners.
“Larger dies are more susceptible to rotational inaccuracies during die placement. A small theta inaccuracy will cause a larger x, y bump placement inaccuracy,” said Amkor’s Kelly, adding that as the distance from the die center increases, it culminates in a maximum inaccuracy at the extreme corners of the die. “If the die is small, the theta inaccuracy may remain the same, but the associated x, y bump placement inaccuracy is reduced.”
Fig. 4: Illustration of different bump densities and x-y displacement. Source: A. Meixner/Semiconductor Engineering
Fig. 5: Illustration of different bump densities, die size, and rotation. Source: A. Meixner/Semiconductor Engineering
Self-aligned bonding methods tolerate some placement error, but that tolerance goes away with the shift to thermal compression and then hybrid bonding. The chip-first flow is even less tolerant.
“If the die are being placed in a chip-first flow, the initial die placement accuracy in x, y, and theta is critical, as there will be no chance for die self-alignment,” said Amkor’s Kelly. “In this instance, the die placement equipment must be more accurate, which is usually more costly and may have a slower throughput.”
Concern regarding throughput continues to be a metric of concern for OSATs. “The need for high accuracy and UPH (unit per hour) placement are important drivers for finer pitch die,” said Mark Gerber, senior director of engineering and technical marketing at ASE Group. “The die size translates directly to the number of dies per wafer. The larger the die, the fewer the die on a wafer. When considering the total line throughput, the placement time can be less for larger die, but the time to switch out new wafer carriers can impact the overall assembly efficiencies.”
Lower throughput translates directly into factory costs in terms of workstation footprint, and tooling numbers. In addition, depending upon the bonding placement error specifications and the number of dies to place, engineers may need to have multiple pick-and-place tools in their assembly line. This increases the potential number of escapes from a pick-and-place tool’s optical checks.
Fig. 6: Multiple pick-and-place tools vs. a single pick-and-place system. Source: Universal Instruments
For bump bonding technologies, pick-and-place tools that can handle multiple die sizes have been available for quite some time. For thermo-compression bonding, pick-and-place tools meet the demands of both pitch and higher placement accuracy. Until recently, however, tools for both multiple die sizes and such high placement accuracy have not been needed. Demand is only now prompting pick-and-place suppliers to develop such tools.
Following placement comes bonding, and those recipes also are affected when bump density differs. “Different bump pitch impacts the distribution of thermal stress during the bonding process. The solutions include adapting exposure time and modifying bump dimension according to the pitch,” said Stefan Chitoraga, technology & market analyst for semiconductor packaging at Yole Group.
A number of other factors need to be considered. “For mass reflow or bulk heating methods, the volume of solder present for solder joints is different, but cannot always be the absolute optimal volume for both a small-pitch, small-diameter bump,” Kelly said. “This arises because plating thicknesses to deposit solder (and Cu) tend to be somewhat different based on bump density, which requires a die-level bump optimization across all the bumps and bump regions to find acceptable volumes of solder. This is currently an active area of development and optimization. Bonding process selection is another variable that can be optimized as well. New local heating methods such as laser-attach methods or thermo-compression attachment methods can help to open up the process window.”
Coping with die height delta
There are many reasons for different die heights. Common ones include thinned versus non-thinned die, and single die versus stacked die. Depending on the product, the die height delta can be relatively small (e.g., 10 to 25μm) or large (e.g., ~200 to 400μm).
Fig. 7: Different die heights. Source: A. Meixner, Semiconductor Engineering
The consequences of die height differences ripple across the assembly flow, affecting bonding recipes, warpage mitigation, and underfill material.
“These differences need an adapted assembly strategy, depending on interconnection method —typically soldering vs. thermo-compression bonding,” explained Tanja Braun, head of System Integration and Interconnection Technologies at the Fraunhofer Institute for Reliability and Microintegration IZM. “For soldering process (i.e., flux dipping and component placement) only mechanical aspects need to be considered. The pick-and-place tool should not interfere with neighboring dies, assemble lower dies first, etc. For thermo-compression and thermosonic bonding, naturally thermal influence becomes relevant. Re-melting of adjacent joints and excessive IMC (intermetallic contact) formation might occur.”
Thermal considerations include the temperature during the bonding process and a product’s thermal management solution.
“For the 2.5D package platform, different die heights can have a number of different impacts on both the assembly process and final product,” said ASE’s Gerber. “For the assembly process, the spacing of the components can create placement limitations where the components need to be spaced further apart, which can impact device performance. Special tooling and placement equipment helps address these challenges. For the final product, different die heights can present challenges for heat spreaders, but in some cases this can be intentional to reduce the thermal impact on nearby die.”
Others agree on the need for good thermal interfaces. “Depending upon the product needs we have multiple mitigation approaches to use,” said Lalitha Immaneni, vice president of architecture, design, and technology solutions for foundry technology development at Intel. “A metallic thermal interface material (TIM) can mitigate the impact of a die height difference because the bulk conductivity of a metallic TIM is high enough that the die height difference will have minimal thermal impact. In the event that a metallic TIM will not meet the product needs, we can manufacture and integrate a stepped integrated heat spreader, which maintains a thin bond line thickness across multiple die height differences. We also have newer metallic/polymer hybrid materials that can mitigate the impact of small/modest die height differences.”
Fig. 8: A stepped integrated heat spreader bridges different die heights. Source: Intel
Warpage and co-planarity remain significant concerns during the advanced assembly process because unevenness can impact assembly yield and long-term reliability.
Dies with different heights inherently exist in different planes, and thereby affect any process step for which low co-planarity variation is desirable.
“Co-planarity remains a big issue,” said Dick Otte, CEO of Promex Industries. “In fact, it’s the biggest single issue when people get 5,000 bumps and they want copper pillars to be more consistent on a chip, and to interface with some kind of substrate. Things better be pretty flat.”
The die height with respect to the die area affects mechanical properties. With multiple die heights greater warpage variation seems inevitable.
“By definition, heterogeneous integration will drive a larger warpage window for chip attach, and that’s something for which we have some solutions in place,” said Sujit Sharan, fellow in advanced design technology for foundry technology development at Intel. “Depending on the process node, you may have different metal stacks in the silicon which obviously warps the silicon differently. Different silicon processes also induce different amounts of warpage. This creates a big challenge to make sure that we can do a good attach, both chip-to-wafer and chiplet-to-substrate. We have warpage specs both for room temperature and chip attach to ensure a good quality chip attach to the substrate which will meet yield and reliability specs.”
Die height differences can further impact both molding and underfill processes.
“With the die-last process, the challenge is to create uniform molding,” noted Tadashi Takano, senior director of chiplets/FCBGA development at Amkor. “Different die heights will lead to different gaps to the mold chassis which may affect the mold flow.”
The underfill process ensures mechanical stability of the bonds between die and substrate. In HPC products, the stacked memory dies sitting near a processor die add new assembly challenges.
Intel engineers recently described how a large die height delta (~ 400 microns) and smaller die to die distance (~100 microns) for a GPU product resulted in an “underfill on die” defect. [1] If not avoided or contained, then overall package thermal performance will be negatively affected at time zero. And if the TIM(s) delaminate from the chip, thermal performance could degrade faster. After experimenting with four possible process modifications, they found one process that met cost goals while containing the defect. “After careful consideration, it was determined that the trench technology provided sufficient process capability at reasonable cost and minimal interaction risk and therefore was selected as the path for HVM,” wrote the authors.
Even assembly processes that embed die into substrates are affected. “A big challenge comes when there is a need to embed dies with different heights into the same IC substrate (i.e. bridge devices),” said Yole’s Chitoraga. “This brings additional difficulties impacting the build-up layer process flow, specifically lower routing density, increased reliability issues, and a 4% to 10% additional yield loss compared to traditional approach.”
Conclusion
By its nature, heterogeneous integration embraces die with different dimensions in the x, y, and z directions, and different bump size and densities. Considering these die dimensional differences requires attention to detail for developing assembly manufacturing processes with a wider process envelope for bump density, die height, and die area. The details in the manufacturing process make the final product.
But the yield, cost, quality triangle becomes harder to achieve when these details are taken into account. Assembly process engineering teams need to continue developing solutions for die dimensional differences along with adopting more standardization to manage these differences. Otherwise, customizing per product will be too time-consuming and costly, affecting time to market and profitability for product segments other than HPC applications.
References
Related Reading
What Works Best For Chiplets
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What Can Go Wrong In Heterogeneous Integration
Workflows and tools are disconnected, mechanical stress is ill-defined, and complete co-planarity is nearly impossible. But there are solutions on the horizon.
Fan-Out Packaging Gets Competitive
Manufacturability reaches sufficient level to compete with flip-chip BGA and 2.5D.
Mechanical Challenges Rise With Heterogeneous Integration
But gaps in tools make it difficult to address warpage, structural issues, and new materials in multi-die/multi-chiplet designs.
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excellent article in terms of detailing and ease of reading