Internet of FD-SOI Things?

Are fully-depleted silicon-on-insulator (FD-SOI) wafers having a moment? Certainly SOI wafers are not new. Soitec’s SmartCut layer transfer technology was patented in 1994, and wafers with implanted oxide layers were available before that. Still, adoption of SOI wafers has been limited. Though they offer improved device isolation and reduced parasitics, the increased wafer cost has been an obstacle.

In some situations, though, the tradeoffs are changing. On one hand, mobile devices and emerging “Internet of Things” applications demand circuits that limit power consumption while maintaining device performance. Yet, for bulk silicon devices, increasing gate leakage and sub-threshold current have made static power consumption comparable to dynamic power consumption. As Claudio Fiegna (professor at the University of Bologna’s School of Engineering) and colleagues discussed back in 2008, dynamic power density is increasing as operating voltage scaling has stalled.

At the same time, process complexity is increasing. Smaller devices require more complex implant structures for isolation and threshold voltage control. Increasing process variability requires larger design margins.

Meanwhile, as bulk silicon device manufacturing has become more complex and expensive, SOI wafers have improved, with thinner top silicon layers, thinner buried oxide layers, and more uniform specifications. Andrzej Strojwas, professor of electrical and computer engineering at Carnegie Mellon, observed that Soitec now delivers wafers with 10nm to 12nm silicon layers on 25nm buried oxide, and has demonstrated +/- 0.5nm silicon and +/- 1nm oxide thickness control. Increased manufacturing capacity has reduced cost and helped to minimize supply concerns. The technology seems to be getting a second look, and designers seem to like what they see.

On the process side, some advantages immediately appear. With a buried oxide layer underneath the transistors, there is no need for deep isolation implants. A fully-depleted thin-body transistor has no channel doping, and therefore no doping variability. Jamie Schaeffer, 22FDX product manager at GlobalFoundries, reports that a 22nm FD-SOI design will use 10% fewer masks than the same design using the company’s 28nm bulk silicon process. Reduced process complexity goes a long way toward offsetting wafer cost concerns. (Although, as IMEC’s vice president of process technologies Aaron Thean pointed out, the very thin silicon layer does raise potential yield concerns. It’s not possible to simply etch away a damaged surface layer and start fresh.)

A bigger reason why FD-SOI is attracting attention now, though, is power management. Improved isolation reduces leakage and therefore static power consumption. With a thin, well-isolated channel, gate control is improved and short channel effects are reduced. The same performance can be achieved at a lower operating voltage, reducing dynamic power consumption. The performance boost is dramatic. Strojwas reported that ARM Cortex-A9 devices at the 28nm node can see a 30% speedup at constant power or a 30% power reduction at constant speed. Olivier Faynot, microelectronic section manager at CEA Leti, described it as “next node performance at current node cost.” Superior performance allows manufacturers to achieve additional savings by extending the life of their current toolsets.

Still, the difficulty of threshold voltage tuning in SOI devices has been a major obstacle for previous generations. Besides providing isolation, all those implant layers allow designers to specify different threshold voltages for different parts of the circuit. In numerous interviews and research on FD-SOI, body bias capabilities came up again and again.

Body bias is not a new technology. Texas Instruments used it for power optimization in bulk devices. In bulk devices, however, the effect has become smaller and less useful as feature sizes have fallen. In FD-SOI wafers, though, the buried oxide creates a capacitor underneath the transistor layer. Bias applied to one plate of the capacitor — the wafer bulk — changes the charge on the other plate, the device channel. For any individual device, Thean said, forward bias improves performance, while reverse bias reduces leakage.

Moreover, the bias can vary dynamically, under control of the circuit. In an SoC device, Schaeffer explained, some blocks might be inactive most of the time, but need high performance for brief intervals. Changing the bias can change the behavior of that block from power optimization to performance optimization. Another area might be active most of the time but have lower performance requirements, making a different bias preferable. Overall, Faynot said, appropriate biasing can add 10% to FD-SOI’s already impressive power savings.

Though FD-SOI wafers offer reduced dopant variability, other sources of process variability exist. Body bias can, for example, help compensate for variable die-to-die and center-to-edge device performance. For example, a small benchmark test could be used to establish a “background” bias.

This does not mean that FD-SOI wafers are going to displace bulk silicon, though. Though they offer substantial advantages for planar transistors, the comparison to finFET devices is less clear. Thean noted that the most challenging aspect of finFET design — the quantization of gate width to an integer number of fins — does offer some benefits. For instance, by making fins taller, designers can increase device area without increasing silicon footprint.

The improved electrostatics of FD-SOI devices help with channel control, but the fact remains that only a single gate is available to a planar transistor. The advantages of multi-gate designs will only become more dramatic as devices shrink. While FD-SOI devices do very well in their power-sensitive niche, they are less competitive for highly performance-driven devices.

It’s also important to remember that not all SOI devices are planar. At 14nm, Faynot said, IBM has demonstrated FD-SOI finFETS, which are easier to etch than finFETs on bulk silicon. The 22nm node is likely to see SiGe PFET devices on SOI, improving the balance between NFET and PFET devices. Beyond 14nm, localized process strain — long established in bulk devices — will be needed for SOI NFETs, too.

So it’s not accurate to say that FD-SOI alone will solve the many problems looming for advanced transistors, but it does appear that it can be part of the solution for power-sensitive applications.