Key Technologies To Extend EUV To 14 Angstroms

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer.

So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry has taken delivery of a high-NA EUV scanner. And efforts are underway at Intel, imec, ASML, IBM, and soon at TSMC, to shore up the resist stack, EUV mask technology, and first processes for the new scanner. The industry also received breakthrough news at SPIE in February, when imec announced it resolved 16nm lines and spaces using chemically amplified resist, and 10nm features using metal oxide resist and high-NA patterning (see figure 1).

Fig. 1: The high-NA EUV scanner printed 16nm features using chemically amplified resist (CAR), but was able to resolve 10nm features using metal oxide resist (MOR). Source: imec

At Semicon West and imec’s technology forum this month, lithography experts from ASML, IBM, imec, Lam Research, and TEL gathered to share the progress and productivity advancements underway for high-NA EUV. From these and other inputs, it seems likely that EUV fabs are poised to adopt metal oxide resist stacks, new stochastic reduction strategies, angular etches, and possibly curvilinear masks to transition from the 2nm device node (22nm pitch) to the 10A node (18nm pitch, 9nm CD) for future large AI SoC and accelerator chips. DRAM makers are expected to adopt high-NA EUV in the 10A node range.

“The roadmap through 2039 clearly shows a need to drop critical dimensions down to well below 20nm pitches, and perhaps out toward 14nm and 10nm pitches toward the end of the next decade,” said Michael Lercel, head of global customer strategic marketing at ASML. High-NA has demonstrated leading performance (see figure 2), including printing 20nm lines and spaces and 30nm via holes. A depth of focus of >50nm and a CD uniformity of 0.6nm was achieved on 28nm lines and spaces.

Fig. 2: 0.55NA EUV produced 20nm lines and spaces or 30nm contact holes. Source: ASML

Print variability control is just as important as being able to print a small feature in the first place. “We see that scaling is moving basically at the limit of what we can do with edge placement error,” said Rich Wise, vice president at Lam Research. He highlights the popular RLS triangle that illustrates the tradeoffs between resolution, R, line-edge roughness, L, “which is also a proxy in some cases for defectivity and yield, and S which is sensitivity or speed. We can essentially deliver on any two of these metrics, but it’s delivering on all three that is the most challenging. Results that focus only on resolution and line-edge roughness often slow the scanner down, which we want to push as much as possible.”

Looking for high NA’s tipping point
Fabs typically time new scanner transitions to when the technological imperative lines up with ROI. “The key driver for dimension scaling is defined by the well-known Rayleigh equation, R = k1λ/NA², where major resolution shrinks are accomplished using shorter wavelength and larger lenses,” said Ru-Gun Liu, vice president at imec. “This was complemented by multi-patterning techniques in 193nm immersion while waiting for EUV to mature and reach a competitive cost, and it is exactly what we see happening again now. High-NA EUV will enable the logic A14 node by replacing a complex and expensive multi-patterning process with a single exposure solution.”

Recent wafer runs show high-NA is up to the challenge for gate-all-around nanosheets. “Direct sheet patterning enables design flexibility and effective gate length scaling with comparable performance to SADP/SAQP patterned sheets,” said Luciana Meli, senior manager of lithography and metrology at IBM Research. She noted that the insertion of single diffusion break (SDB) at cell ends is a key scaling knob that enables a similar design flexibility as that available with finFETs.

Meli noted that an outstanding need with high NA involves reducing feature tip-to-tip spacing. She said MOR resist platforms can help in this regard, extending tip-to-tip spacing to 22nm, notably, with higher yield than that obtained using CAR platforms. Even so, a cut mask is needed to meet a 20nm specification.

But the greatest challenge with high-NA appears to be caused by the smaller exposure field size. Because the lens on the high-NA EUV optics shrinks features on the mask by 4X and 8X in the x-y directions (anamorphic lens), the field size on the wafer is half as big as that for 0.33NA EUV and 193nm lithography (26 x 16.5mm vs. 26 x 33mm). The two exposure fields must be stitched together precisely.

In-die stitching is a big deal. And stitching optimization around the design, mask, optical proximity correction (OPC), process, and scanner settings is just one high-NA specific challenge. Because SRAM chips have stopped scaling and SRAM can consume up to 50% of an SoC’s area, only a stacked chiplet solutions can avoid high-NA EUV and stitching.

IBM’s Meli pointed out that challenges arise from the combination of high-NA EUV layers with full field 0.33NA layers, including overlay errors between blocks and the metal stack.

Imec and partners are developing at-scale in-field stitching methods that will reduce the need for designs need to cope with the field size reduction. Another technology imec is pursuing for high NA EUV involves the use of directed self-assembly (DSA) to reduce roughness and defects and lower dose. The first step involves scaling DSA patterns below 24nm pitch with a switch from the industry’s current PS-b-PMMA-type of block co-polymers to so-called high-χ block co-polymers.

Imec also has demonstrated progress in developing a low-n mask absorber that enables performance improvements in the form of wider process window and a 20% dose reduction for lines and spaces without increased roughness or stochastic failures (see figure 3). The R&D organization also found that tip-to-tip dimensions were not negatively impacted by the dose reductions, which directly impact scanner throughput. Greater reduction in LWR/LER on masks are also in the works, because roughness translates to even more roughness on wafers.

Fig. 3: A new low-n absorber in the EUV mask improves the process window and lowers dose. More progress is needed in at scale stitching, reducing mask variability, and carbon nanotube pellicle development. Source: imec

The high-NA scanner itself was designed for higher productivity, including faster reticle and wafer stages, a more powerful CO₂ laser source, and more efficient photon conversion efficiency, thereby boosting the scanner throughput.

“To accelerate the raw throughput we wanted to increase the power out of the drive laser, but also wanted to increase the repetition rate of the source,” said ASML’s Lercel. “So an EUV source accelerates individual tin droplets across a vacuum chamber, and they are being hit by high-power infrared lasers. That happens today at 50,000 times per second. With the new high-NA EUV system, we moved up to a 62 kilohertz repetition rate, and the higher power of 500 watts allows us to deliver 220 wafers per hour throughput, which is a key enabler.”

Ongoing industry concerns over the high energy use of EUV scanners has driven changes. Each generation of EUV scanner has reduced the energy consumed per wafer processed. In 2023, the energy use per exposed wafer is 42% of what it was in 2018. Availability of the tools is 93%.

Reducing stochastics

As features scale, roughness becomes a greater portion of the whole feature dimension. LER and LWR can account for 50% of edge placement error at the 3nm node. Allowable edge placement error is only between 5 to 6nm at the 2nm node, and is expected to drop to 4.5nm for the 1nm node (see figure 4).

This process variability eats into the process window and causes electrical failures due to bridging between lines, fragmented lines that break, via holes that close up, or neighboring holes that merge. As a result, lithographers and etch teams continually develop strategies to reduce EPE, which is a bucket term that covers overlay (layer/layer offset), CD uniformity and stochastics.

Fig. 4: Allowed variability (edge placement error) shrinks with achievable resolution. Source: ASML

Another way to look at this is in terms of useful process window. A high yielding patterning process is defined by what is called the “failure free latitude,” which refers to the smallest feature you can print without seeing lines break, and the largest feature you can print without seeing lines merge. This is characterized by both a focus window (DOF) and an exposure window.

“In many cases as you scale pitch you see this latitude go to zero, so to help that scaling continue, we co-optimize a dry metal-oxide photoresist and its underlayer to reduce the tradeoffs between resolution, LER and sensitivity. That underlayer helps accelerate the activation of the resist during post processing, especially during the bake,” said Lam Research’s Wise.

MOR vs. CAR materials
Spin-on chemically amplified resists are the workhorse material in 193nm immersion (193i) and EUV patterning, but dry photoresists have come on the scene in recent years in new chemical formulations, so-called metal oxide resists (MORs). MORs are offered by JSR (formerly Inpria) in spin-on form, and by Lam Research as a dry system.

Performance advantages of the dry (CVD-based) resist processes include higher absorptivity than organic materials and limited possibility of pattern collapse. “There’s also the opportunity to optimize the subsequent transfer etch, either in situ or ex situ, to eliminate things like defects and linewidth roughness. And it’s very tunable in terms of thickness or even changing the process from the top of the resist to the bottom of the resist,” said Wise.

Lines and spaces of 12nm (24nm pitch) have been fabricated using dry resist on a 0.33NA scanner. An added plus is that material waste can be 5 to 10X lower with dry resist stacks relative to spin-on wafer track photoresist processing. The imaging stack includes resist, underlayer, and hard mask (for example, PECVD carbon, silicon nitride or SiOC) on the silicon.

Regarding the transfer etch into the hardmask layer, Wise disclosed that Lam Research recently developed a more powerful plasma source that provides more efficient dissociation of species in the plasma. “The reason the transfer etch is so critical is because we use that etch to correct some of the stochastic defects that are coming into the pattern transfer.”

Another innovation in etching technology involves changing the angle between the 300mm wafer and the plasma source, a feature available from all major vendors. So-called lateral or angular etching address the need to reduce tip-to-tip spacing without using a separate cut mask exposure and etch step. Such etches also have the potential to reduce tip-to-tip variability across a die, thereby improving yield.

Tomonari Yamamoto, a TEL fellow, described his company’s directional CD modification process using a new etch source and tilting wafer stage. Changing the angle in the system can adjust the lateral etching rates to fabricate ovals or other structures without having to use double patterning. The new source also aims to reduce scumming defects and reduce pattern roughness.

But the more significant result from such systems may be reducing roughness and stochastic defects that cannot be addressed in other ways, while providing the capability to expanding features in the y direction. “An angular etch beam is applied to push the line tip-to-tip spacing and reduce the roughness of the line/space pattern,” said imec’s Liu. He refers to the technique as trans-patterning, noting that it potentially can be used to stretch a contact hole into an oval structure or even a hole into a line. “People can use this technology to change a pattern from hole to line with further pitch reductions — just like the Transformers,” which inspired the name trans-patterning.

Liu cautions, however, that these are early days. “This is just the beginning of the trans-patterning related studies because the value and feasibility are still under investigation in terms of the process, OPC, design compliance, EDA, cost effectiveness, etc.”

Another process modification that Lam’s Wise discussed involves the use of a selective passivation layer, followed by etch, to reduce LER and LWR. Wise describes the case of addressing small bits of photoresist that appear as scum or footing at the base of lines. “Across a wafer, we can see defects like this, but by using our new source and depositing a passivation layer that adheres well to the fully formed photoresist lines but poorly to these scum areas, we can break through and remove these defects.” The passivation process also helps smooth LER and LWR.

TEL’s Yamamoto presented results with spin-on metal oxide resist, showing that MOR — particularly with a new developer chemistry — can improve the process window and reduce feature roughness on 24nm pitch lines and spaces. Relative to CAR resists, the MOR also offered greater resistance to pattern collapse at smaller feature size. He further stated that the thin photoresist required for high-NA EUV more easily suffers from stochastic defects.

The underlayer to the EUV resist plays a critical role in the scalability of the process, according to Joyce Lowes, director of emerging materials technology at Brewer Science. To assist with pattern transfer, underlayers need to provide superior etch resistance to their predecessors in an even thinner layer. The underlayer additionally needs to adhere well to hard masks and silicon, while performing with a wide process window with no increase in pattern defectivity.

Curvilinear structures
It seems likely that curvilinear patterns will become necessary as devices require shorter connections between devices. Curved structures enable shorter links between layers and between lines in the same plane.

“We propose and demonstrate that incorporating curvilinear shape in design can reduce manufacturing costs and enhance the power and performance of the chip,” said imec’s Liu. Additionally, we plan to use curvilinear design to increase transistor density. We have developed a method of using curvilinear design in a standard cell with enabling design verifications such as design rules, design rules verification, RC extraction, and finding OPC solutions.”

The availability of almost unlimited computing resources applies to the mask writing process for EUV masks. Together with multi-beam mask writers, optical proximity correction (OPC) mask processes are speeded up considerably. A curvilinear mask can be written in the same amount of time that it takes to write an orthogonal mask.

Experts indicate the industry may be approaching the tipping point for curvilinear (curvy) mask patterns. “Curvilinear patterns already are being used today in production masks for both 193i and EUV,” said Aki Fujimura, chairman and CEO of D2S. “But different companies use it differently. Some companies use it only in hotspots on the chip where it is needed.”

Full die/wafer curvilinear implementation will be enabled by standard EDA integration. But first, there needs to be a convention for measuring the uniformity of curved features. “When it comes to a software correction tool, you’re doing some correction to try to get the actual shape to come out the way you design,” said Fujimura. “With Manhattan features (orthogonal), the industry determined standard methods some time ago for measuring CD and CD uniformity. We don’t have such a convention for curvilinear structures, so how do you compare contour to contour, for instance? That has not been established yet.”

Nonetheless, fabs are moving forward. “At a recent Synopsys Tech Forum, TSMC discussed their substantial GPU infrastructure, highlighting their ‘large farm of GPUs’ and their plans to expand this capability further due to the benefits GPUs offer, especially for processing that involves curvilinear mask shapes,” added Fujimura.

Conclusion
It’s an interesting time to be working at the leading edge, where engineers can print and control 10nm features. Looking forward to the 18A to 14A nodes, standard EUV (0.33 NA) likely will be extending as long as possible through multi-patterning, with many evolutionary advances in tooling, materials, and masks that work synergistically to pattern and etch devices at scale.

At some point, the industry seems poised to adopt new photoresist platforms built around metal oxide photoresists, underlayers, and development processes — either wet, dry or both — which will work together with new etching platforms to extend CD and reduced stochastic defects through a combination of strategies.

For high NA, in-die stitching is in its infancy, a brand new technology caused by the anamorphic lens, and a new absorber material in the mask is expected to expand the process window. It seems that each development that advances performance and throughput without degrading other key metrics will find its way toward production use.