Litho Options Sparse After 10nm

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in , chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm.

So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—DSA, EUV, multi-beam e-beam, nanoimprint, and 193nm immersion with multiple patterning.

Not long ago, chipmakers were confident that EUV would be ready for 7nm. But now, the industry is not as bullish about EUV amid ongoing issues with the technology. For example, Intel listed EUV as its top option at 7nm, but the company recently said it could develop the process without EUV. Apparently, Intel found that it’s more cost-effective to use 193nm immersion and multiple patterning.

Still others continue to develop EUV for 7nm, but many are hedging their bets and developing backup plans. The main backup is immersion/ multi-patterning. “You have to look at both an optical and an EUV path,” said Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries. “Everyone is looking at both options at 7nm.”

Beyond 7nm, there are even more uncertainties about lithography. It’s too far out to make a prediction about 5nm and beyond. By then, chipmakers may implement various 3D architectures, many of which don’t require advanced lithography.

Complementary litho
As before, the decision to use one patterning technology over another comes down to cost and tool readiness. Methodology is also key. In this area, many, if not all, chipmakers are currently deploying what Intel lithography guru Yan Borodovsky calls “complementary lithography.”

In this technique, the first step is to make lines or gratings on the device. For this step, chipmakers will use today’s 193nm immersion scanners. Then, the hard part is to cut the lines into exact patterns with precise accuracy. For this, chipmakers would prefer to use a next-generation lithography (NGL) technology, namely extreme ultraviolet (EUV) lithography and multi-beam e-beam.

Until recently, chipmakers hoped to use EUV for the cuts and other steps at 10nm. But amid delays for EUV, the industry must now resort to the old standby—immersion/multi-patterning. “At 10nm for sure, it’s going to be multiple patterning,” said Girish Dixit, vice president of process applications for LAM Research. “Multiple patterning is here to stay for a while.”

For 7nm, however, the market is up for grabs. There are still several variables, including the timing of 7nm and the progress of NGL. Intel, for one, hopes to take production tool deliveries for 7nm by 2017, according to analysts. Intel’s 7nm process could ramp by 2018. The other foundries could be a year or two behind Intel.

To insert an NGL, the technology must be ready by at least two years before a node ramps. So for 7nm, EUV and multi-beam must be ready by the 2015/2016 timeframe or so. But if chipmakers delay 7nm, NGL could get some breathing room.

In any case, there are still uncertainties with NGL, particularly EUV. “With EUV, everything has been fixated on how many wafers it can process in a day,” Dixit said. “But the rest of the ecosystem must be considered in term of resists, masks as well as pellicles, if they are needed. There is work going on in all of those areas. The question is if all of these things can intercept within the 7nm timeline.”

As a result of the uncertainties, IC makers are looking for ways to extend 193nm immersion and multiple patterning down to 7nm. In reality, 193nm lithography reached its limit at 40nm half-pitch. Chipmakers have extended optical by using an assortment of resolution enhancement techniques (RETs) and multiple patterning.

Basically, there are two main categories of multiple patterning—pitch-splitting and spacer. Pitch-splitting requires separate lithography and etch steps to define a layer. This is called litho-etch-litho-etch (LELE). Meanwhile, spacer, or self-aligned double/quadruple patterning, involves several steps to define a spacer-like feature.

Generally, chipmakers will use a combination of multiple patterning techniques at both 10nm and 7nm. “Spacers are great for making lines,” said Christopher Bencher, a member of the technical staff at Applied Materials. “But eventually, those lines need to be cut. So you would maybe have litho-etch-litho-etch to cut those lines. Vias will also use litho-etch-litho-etch or litho-etch to the nth power.”

Still, the big question is whether multiple patterning is economical at 7nm. With this technique, the number of lithography steps will increase from six at 28nm to eight at 20nm, according to ASML. But that number is expected to jump to 23 lithography steps at 10nm, and a whopping 34 steps at 7nm, according to ASML. “(At 7nm), some of those layers require 12 exposures and the (number of) metrology steps go through the roof. I am not saying this is not possible. Certainty, this is possible,” said Martin van den Brink, president and chief technology officer at ASML. “But if you compared it to the EUV process, it would simplify it.”

Chipmakers could make optical less strenuous using various techniques. “It’s more of a methodology,” Applied’s Bencher said. “It applies to 14nm, 10nm and 7nm. It involves (chipmakers) asking the following questions: ‘What can we do with the existing lithography equipment? What are the self-aligned schemes we can deploy? What’s the patterning capability rule book?’ And then designers can work from there.”

Some can deploy this methodology easier than others. For example, Intel’s separate design and manufacturing groups can work on the issues under the same roof. Intel also simplifies the flow by using uni-directional layout schemes. “They can co-optimize the design rules for the lithography techniques,” Bencher said.

Pure-play foundries face a different set of challenges. They work with a multitude of customers using both uni-directional and more complex 2D layouts. In this case, several factions must get on the same page. “It’s like an orchestra,” Bencher said. “Many people must contribute. For example, you sit your designers down and say: ‘You have to change your libraries to get us from three cuts to two cuts.’ In other words, you identify your snapping points and rally your designers around that.”

There are other considerations as well. “Today, we are doing 16nm/14nm, and then going to 10nm and 7nm,” Lam’s Dixit said. “What’s also important is to make sure you reduce the variance in all of the processes. And at those dimensions, the question is can you get things manufactured with tight enough controls? We talk about process capabilities. But there is not nearly as much talk about process control.”

Where’s EUV?
Compared to optical, EUV could simplify the line-cut process at 7nm. At 7nm, though, chipmakers may also need to use EUV with multiple patterning. So where, exactly, is EUV? Last year, ASML shipped its first production-worthy EUV scanner. The 13.5nm wavelength tool, dubbed the NXE:3300B, has a numerical aperture of 0.33 and a resolution of 22nm half-pitch.

As before, there are still issues with the EUV power source. Until recently, the EUV source generated less than 10 watts of power, making EUV impractical for mass production. But in the second quarter of 2014, ASML shipped its 40-watt upgrade for the EUV source. With the upgrade, the NXE:3300B is producing about 600 wafers a day at two customer sites, according to ASML. (ASML uses a new metric—wafers a day—to quantify EUV throughputs. Previously, the throughput was measured by the wattage of the EUV source.)

Still, chipmakers want a throughput of 1,000 wafers a day to make EUV feasible for mass production. To bring EUV closer to this figure, ASML hopes to ship its 80-watt source by the end of 2014. The 80-watt source will enable a throughput of nearly 800 wafers a day. But still, the 80-watt source is a year or two late to the market and chipmakers are becoming increasingly impatient. “It’s critical that we reach a milestone of 80 watts at customer sites,” said GlobalFoundries’ Mangat.

Then, by late 2014 or early 2015, ASML plans to ship a new version of the NXE:3300B. The so-called NXE:3350B has similar specs as the NXE:3300B. But the NXE:3350B incorporates ASML’s FlexPupil technology, enabling a custom pupil configuration within the system. “The 3350 gives you 1,000 wafers a day,” ASML’s van den Brink said. “One thousand wafers a day is on the threshold that people start feeling comfortable using this in production.”

Other NGLs
Another candidate for line-cut applications is multi-beam e-beam. One company, Multibeam, is preparing its multi-beam e-beam technology for 7nm. Instead of patterning all layers, Multibeam’s so-called Complementary E-Beam Lithography (CEBL) technology is targeted for line-cut applications, primarily in uni-directional layouts. “1D line and cut layouts have been in use in manufacturing of advanced designs for some time,” said David Lam, chairman of Multibeam. “The rate of adoption will accelerate.”

Besides EUV and multi-beam, nanoimprint is another NGL. One company, Canon Nanotechnologies (CNT), is developing a new nanoimprint tool, primarily for non-logic applications. Another NGL, directed self-assembly (DSA), is the dark horse. When used in conjunction with a pre-pattern that automatically directs the orientation of the block copolymers, DSA can reduce the pitch of the final printed structure.

DSA could be ready by 7nm or 5nm. “DSA could do single hole contact shrinks. But we could always do that with (today’s spacer technology). To me, that doesn’t look very interesting for DSA,” Applied’s Bencher said.

DSA, however, could get some traction in pitch multiplication applications. “You have a big slot and you are trying to get three holes into the slot. That’s enabling. But we are a long way from having the positional accuracy of all of those holes being exactly where they need to be,” Bencher said.

What’s after 7nm?
Beyond 7nm, there are more questions than answers. It’s unclear what the devices will look like by then. Another question is whether NGL will play a role at 5nm and beyond. But if NGL never pans out, can the industry extend optical lithography to 5nm and 3nm? “It’s possible in theory,” Lam’s Dixit said. “But at these dimensions, you are not just talking about the feature. You might have a process and make a feature at 5nm. But can you make 5nm features on wafer number one, wafer number two, wafer 25 and then across all die?”

Others agreed. “Immersion can extend farther than people think,” Applied’s Bencher said. “We can spread out the pain across many, many years and go from two masks to three masks and to four masks. But eventually, the tolerances stack up too much and your yields suffer. What’s going to determine the end of propagating multiple patterning is the tolerance stack-up (effect).”