Machine Learning Enabled High-Sigma Verification Of Memory Designs

Emerging applications and the big data explosion have made memory IPs ubiquitous in modern-day electronics. Specifically, the demand for memories with low-die area, low voltage, high capacity, and high performance is rising for use by data center and cloud computing servers. This is essential to serve the exponentially growing connectivity boom and the latest emerging 5G based systems, including those targeting telecommunications and automotive applications.

Memories in the form of embedded memory IPs in a system-on-chip (SoC) account for a significant portion of the chip – over 50% in some applications. These memories store and release vast amounts of data across the high-speed network and the internet, to and from numerous edge devices. Memories by design have many replicated building components such as bitcells, sense amps and control logic. Robust verification of these memories necessitates high-sigma analysis to account for all design variations and meet the power, performance and area requirements to achieve the targeted design yield.

Most of today’s conventional high-sigma analysis methodologies are not scalable and accurate enough to meet production design quality and schedules. This presents several challenges for memory designers and design teams and introduces uncertainty and risk that ultimately impacts memory design yield and consequently, the quality of the end product.

Mentor, a Siemens Business, provides comprehensive, fast and accurate high-sigma analysis and verification of the memory components and the full-chip memory. Solido Variation Designer’s High-Sigma Verifier tool uses machine learning technologies to intelligently verify to 6 sigma and higher, with sign-off Monte Carlo SPICE accuracy in only a small number of simulations. Solido Variation Designer’s Hierarchical Monte Carlo tool achieves fast and accurate full-chip memory verification using hierarchical, structurally-correct Monte Carlo samples.

High-sigma verification challenges for memories

The high number of memory component replications requires high-sigma verification to perform exhaustive variation-aware simulation for each component and identify the worst-case failures.

This presents several challenges. Brute force high-sigma verification requires millions and billions of simulations, which is not feasible for production simulation runtimes (figure 1). Thus, designers are compelled to consider other shortcut approaches, such as running a smaller set of Monte Carlo simulations and using extrapolation techniques to go out to the high-sigma region. One method is using +/- 6 standard deviations from the mean. This is prone to producing inaccurate results as it assumes a perfect Gaussian distribution, which may not be the case.

Fig. 1: Reaching high-sigma is not practical with brute force Monte Carlo simulation.

After performing the high-sigma simulation at the memory component level, the designer has to account for the statistical variation of the full-chip memory. Verifying global variation and multiple levels of local/mismatch variation at the same time is essential to achieve accurate full-chip memory yield. This is an incredibly complex task and, currently, designers are not able to do this with statistical accuracy.

Running Monte Carlo simulation on the full-chip memory design is time-consuming and impractical, taking weeks or months. Thus, memory designers settle for a small number (e.g., 5-10) of full-chip simulations. They then over-margin the design to compensate for potential uncertainty that comes from not correctly accounting for the statistical variation of the full-chip memory design. This leads to sub-optimal power, performance and area for the memory design.

High-sigma verification for memories

The Solido Variation Designer solution provides advanced variation-aware design and verification tools. At the core of the tools are machine learning technologies enabling production-proven fast and verifiable brute force accurate high-sigma Monte Carlo simulation. The High-Sigma Verifier (HSV) and the Hierarchical Monte Carlo (HMC) tool flow provide fast and accurate variation-aware verification of the memory design.

HSV is a next-generation high-sigma solution that intelligently verifies the memory components (e.g., bitcells, sense amps and control logic) to 6 sigma and higher, with sign-off Monte Carlo SPICE accuracy in only a small number of simulations. It automatically chooses the optimal number of initial Monte Carlo samples to build and verify a machine learning model. Subsequently, it runs an optimal amount of simulations to automatically verify the results are brute force accurate, making it extremely fast. The built-in automation enables the designer to find the yield of the components in a single pass without any manual intervention.

With the Solido Hierarchical Monte Carlo (HMC) tool, memory designers can combine the memory components across the memory hierarchy to achieve fast and accurate full-chip verification.

HMC takes a reduced testbench that can represent the full-chip memory or instance i.e., critical path or memory slice (figure 2), enabling a significantly faster simulation runtime than simulating the full instance or full-chip memory.

Fig. 2: Representing a memory slice.

Achieving full-chip memory yield, for example, of 3 sigma requires that the replicated components within the memory chip are verified at a much higher sigma (figure 3). HMC generates hierarchical, structurally-correct Monte Carlo samples from the memory slice testbench, and enables orders-of-magnitude faster simulation with brute force SPICE Monte Carlo accuracy.

Fig. 3: Achieving 3 sigma, full-chip memory yield.

High-sigma memory design verification flow

Top semiconductor companies and foundries are using HSV and HMC to achieve robust variation-aware verification of the full-chip memory. Using HSV, designers quickly verify the memory components to reach a high-sigma target with verifiable brute force accurate results. With the HMC tool, designers combine all the memory components and achieve a fast and accurate full-chip memory yield using a simplified memory slice testbench with perfect SPICE Monte Carlo accuracy

Consider a case study from a memory column testbench that consists of 32 sense amps per chip and 128 bitcells per sense amp, where a cell current below 410nA is a failure. Given the number of components described, achieving a 3 sigma chip yield requires the bitcell to yield 4.97 sigma. Figure 4a shows the result of HSV. For this result, the output value at 4.97 sigma is 474.1nA, which is well within the 410nA specification. HSV achieves this with a significantly reduced number of simulations compared to brute force, delivering a 3.37M times speedup. At this point, we’ve completed the critical step of verifying the component (bitcell) and are ready to perform the final full-chip verification step using HMC.

Figure 4b shows results from running the same memory column testbench through HMC. Looking at the 3 sigma chip yield target, we see that the value is 424.7nA, within the 410nA cell current specification. This accounts for all the global and local/mismatch variation effects.

Fig. 4a: Verifying the bitcell to 4.97 sigma.

Fig. 4b: Verifying the full-chip memory to 3 sigma.

Summary

Memories embedded in SoCs require high-sigma verification to achieve high-yield silicon. Traditional brute force Monte Carlo simulation of memory components and full-chip memory is not feasible. Other conventional verification methods and solutions are constrained and do not account for all global and local/mismatch statistical variation, leading to uncertainty and over-margining. This potentially impacts and compromises the performance and competitiveness of the memory product. A comprehensive, fast and verifiable brute force accurate high-sigma verification solution that accounts for all the statistical variation across the memory components and hierarchy of the full-chip memory is essential.

Mentor, a Siemens Business, provides a tool for comprehensive, fast and verifiable brute force accurate high-sigma analysis and verification of the memory components and the full-chip memory. Solido Variation Designer’s next-generation High-Sigma Verifier tool uses machine learning technologies to intelligently verify to 6 sigma and higher, with sign-off Monte Carlo SPICE accuracy in a small number of simulations. Solido Variation Designer’s Hierarchical Monte Carlo tool achieves fast and accurate full-chip verification using hierarchical, structurally-correct Monte Carlo samples.