Reflections On 2015

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with Semiconductor Engineering. We like to hold people’s feet to the fire, but while the “Pants-On-Fire” meter may be applicable to politicians, we like to think of it in a more positive light.

If you wish to refresh your memory about the predictions, they were categorized under New Markets, Tools and Flows, Manufacturing and Packaging, and Design. In each case, the original comment is inserted in italics, often compressed, with their reflection after. Not all contributors chose to provide comments about their predictions.

Graham Bell, vice president of marketing at Real Intent started things off by predicting “approximately 5% to 7% growth in semiconductor business for 2015 and 12% in the pure-play foundry business, and that leading pure-play foundry TSMC will grow faster than the industry average and in 2015 its business will surpass that of all other pure-play foundries combined.”

The market stalled dramatically at mid-year. Semiconductor growth will be zero +/- 1% for 2015 overall and the foundry sector will grow roughly 5%.

His prediction did come true that TSMC would grow faster than the industry average and in 2015 its business would surpass that of all other pure-play foundries combined. Despite economic headwinds, IC Insights expects that TSMC will grow 11% in 2015. TSMC owned 55%, or $27.8 billion, of the $50.1 billion foundry sector, and established its market dominance (again).

There were lots of predictions about 28nm. Marco Casale-Rossi, product marketing manager within the Design Group of Synopsys, said “28nm will have a very, very long lifespan. This will be strengthened by FD-SOI, which may be a very compelling solution if supported by foundries.” He also said that “10% of design starts will be at 28nm and below in 2015.”

Actually, fewer than 10% of design starts were at 28nm and below in 2015, but 40% of silicon real estate manufactured in 2015 was at 28nm and below. The breadth of active technology nodes widens, and adoption becomes asymmetric. Foundries are expanding their offering at 28nm, and are working on 22nm FD-SOI. In fact, 22nm planar, and not 28nm is the last single-patterning technology node, with expectations there will be yet one more planar node for FD-SOI. However, guess what technology node has and, according to IBS, will continue to have the lion’s share of design starts in the next decade? It’s 180nm, with 25% of all design starts every year from now until 2025.

Two other Synopsys veterans, Rich Goldman, formerly vice president of corporate marketing at the company, and Navraj Nandra, currently senior director of marketing for DesignWare Analog and Mixed-signal IP, added some of the reasoning. Nandra stated that “the trend here is that some SoC developers are staying on 28nm rather than moving to finFET technologies due to costs or re-tooling their EDA and IP flows.”

The demand for the 28nm node continues, driven by applications such as low-end smart phones, “action” cameras, set-top boxes, digital TV and SSD’s. To help differentiate, enhanced versions of the 28nm node are being offered to the market that will satisfy both the higher performance and lower power needs of emerging applications such as smart watches. One example of this is TSMC’s 28HPC+ technology. Integrated circuits for automotive requirements such as ADAS and infotainment are likely to be 28nm or finFET candidates in the 2020 timeframe. One of the reasons is that once the automotive chip design team has decided on a process node, the qualification process that includes burn-in takes much longer than for consumer devices, thereby extending the process life.

Not all the focus will be on 28nm, however. automotive and (IoT) are extending the life of the “established nodes” with options such as thick-oxide libraries for leakage improvement, improved electromigration performance on the interconnect, and embedded flash, on 90nm, 55nm and 40nm. In the finFET realm, while production tape-outs are now happening, the most interesting development in 2015 was the announcement of “compact” offerings from TSMC and Samsung – bringing the cost to a point that accelerates the move to finFET.

“The high-risk, high-reward transitions to new nodes at 16/14nm will be moving very quickly to 10nm and then 7nm,” observed Chi-Ping Hsu, senior vice president, chief strategy officer for EDA at Cadence.

With more than 100 companies designing in finFET technology, it is apparent that the race to access the most advanced process technology has not slowed as some predicted. Coupled with significant progress on 7nm development (and 5nm preliminary results already coming in) and the insatiable desire for integration of new capabilities, this trend will continue forward at a rapid pace.

Bell looked at what he expected to happen in the memory industry. “We will see Samsung in volume production for 16/14nm DRAMs, followed at the end of the year by Micron and SK Hynix. For NAND flash we see a more aggressive roadmap, with 16/14 already at volume. The transition to 12/10nm processes will take over at the end of 2015.”

The NAND process roadmap from TechInsight confirms some of his predictions for 2015. For 3D NAND flash, Samsung announced volume production of its memory in 2015 with a total stack of 48 cells, and this development confirms it is on track. The 16/14 nm node is already at volume.

NAND process roadmap from TechInsight

For the DRAM process roadmap Bell predicted Samsung would be in volume production for 16/14nm DRAMs, followed at the end of 2015 by Micron and SK Hynix. Micron is on track to support the 1X node according to the following graphic.

Micron Technology Roadmap, Aug. 2015

There were hurdles to get to these new nodes. , president and CEO of Solido Design Automation, said that “manufacturing variation will become increasingly problematic in 2015. To ensure optimal design, development teams will focus both on resolving the increasing number of variation issues, and on reducing the simulations required.”

Variation has indeed become a must-solve problem at sub-16nm. Local mismatch for analog or SRAM blocks needs to be considered in the design process. Trying to do yield analysis after the fact is too late. There is also strong interest in EM/IR analysis at the block level at deep design nodes. Here, too, there is interest in finding faults early, such as during the layout stage to make sure there are no missing vias resulting in a hot spot.

Packaging
Hsu predicted that “the lines between PCB, package, interposer, and chip are being blurred.” Hsu was looking for design environments and analysis tools where cross-fabric structures could be created and optimized.

The innovation opportunity in the packaging space has accelerated. Integration via new process technology is not the only avenue for achieving integration goals. Just open up some of the latest gadgets and you will see marvels of integration in multi-die, silicon substrates with multi-layers and flexible interconnect. These multi-fabric structures have driven the rapid adoption of analysis tools for power and signal integrity.

New classes of design kits are being created to provide a homogeneous solution to the heterogeneous problem. In 2016, expect the same rapid growth.

Hsu also predicted that “the foundry encroachment into the OSAT (outsourced assembly and test) space has begun with silicon-based 2.5D interposer technology and through-silicon via (TSV) 3D die stacking offerings. As the pitches get finer on organic substrates and pricing on silicon options comes down, the foundries and the OSATs will be on an innovation spree to vie for dominance.”

Foundries crossed some key cost point hurdles in 2015 for high-speed, high-pin-count multi-die integration offerings. Wafer-level fan-out solutions are now practical from a cost standpoint for a broad set of products. The traditional OSATs have made infrastructure investments of their own to extend their reach into finer and finer pitch manufacturing capabilities. There also has been a rise in customer customization capabilities to enable end-products to achieve more desired form factors. Interest from the systems companies has peaked, and the result is innovation across the chip-package-interconnect-board spectrum.

Markets and politics
Bell made an interesting prediction based on the removal of tariffs with China. He said that “China certainly wants to promote its high-technology sector. However, big companies such as Lenovo and Huawei that are headquartered in China found themselves at a disadvantage when trying to compete with foreign companies on product cost. Both of them rely on imported ICs to build their systems.”

Bell continued that this will benefit large electronics systems companies, but that “with customers turning to foreign suppliers that can offer more leading-edge processes, SMIC may be forced into a consolidation with another leading pure-play foundry.”

This kind of economic transition often results in winners and losers. He suggested a big loser could be China’s semiconductor foundry sector. SMIC is the leading Chinese foundry, with approximately 40% of its business from domestic customers. Its revenue in terms of dollars-per-wafer is much lower than other leading foundries because more than 80% of its business is in geometries larger than 45nm. If customers had turned to foreign suppliers that can offer more leading-edge processes, SMIC might have been forced into a consolidation with another leading pure-play foundry. This did not happen. For 1H2015, SMIC’s revenue was up 9%, and gross margin had improved to 30%. For advanced nodes below 45nm, their growth this year is expected to be 66% over 2014 growth, according to IC Insights.

The bottom line, and good news for consumers, is that all those tech gadgets made in China would cost even less in 2015. This has been the case with a strong U.S. dollar. For example, there is a lot of competition for low-cost quad-core notebooks in the $200 price range.

Design
In terms of how technology is put to use, Hsu predicted that 2015 would be a watershed year, pointing out that “years rarely offer an earth-shaking technological moment but they are more likely to represent the fruits of long labor in various ways.”

2015 did indeed yield the fruits of long periods of labor. The EDA-IP-semiconductor ecosystem has coalesced into a tighter, more cohesive and efficient structure. This ecosystem initially focused on a PC-centric world. Then it shifted to enable an era of infrastructure innovation and deployment, then to mobile, and it is now in the nascent stages of a vast and exciting era of wearable technology. After decades of setting the stage, the near future will see an extremely rich rollout of capabilities that leverage the past investments.

Looking at the innovation award winners from CES in various categories, for example, there was an interesting array of ideas that provided either new twists on established ideas or introduced brand new ideas in the first generation stage. These new innovation branches will drive the volumes of growth in the industry.

, chief executive officer of Breker, identified one design trend. “System on chip (SoC) with one processor is moving to multiple processors with cache coherency. Coherency will be required beyond the CPU clusters, as GPUs, DMA engines, application processors, and I/O devices will all have to be coherent to some extent. Three-level caches will dominate, and all on-chip buses, interconnects, and on-chip networks will support cache coherency.”

This has proven to be the case with many SoCs with several or even dozens of processors having been announced, nearly all with multi-level caches. Many of the IP vendors supplying interconnect buses and fabrics released cache-coherent versions this year. One result is that coherency verification is now the problem of the SoC integrators, not just CPU designers.

Hsu added, “One of the key shifts will be from away from a central processing unit (CPU)-centric approach to architectures that are centered on streams of data.”

Looking at the number of processor units on SoCs, we can see that 2015 offered the continuation of the multi-core, GPU and DSP architectures. Fast and small pairings of processors (such as ARM’s big.LITTLE) with compatible instruction sets, became very popular. So did specialized, programmable processors with optimized execution units and instructions sets. These custom processors are hard not to find in electronic products today. Good examples of specialized processors can be found in automotive ADAS applications. The datacenter is another good example of active architectural innovation where specialized processors are embedded in SoCs and FPGAs.

The next part of this reflection on 2015 will continue by looking at system complexity predictions along with tools and flows for their design.