Rethinking Ethernet For The AI Scale-Up Era: Inside ESUN

Every generation of AI infrastructure has redefined what “the network” means. In today’s training clusters — scaling from hundreds to hundreds of thousands of accelerators — the interconnect is no longer a supporting actor. It has become a first-order determinant of system throughput, utilization, and cost per token. Accelerators inside these systems don’t just move data; they synchronize on it, step after step. When even a small fraction of that traffic is late, expensive compute sits idle waiting.

That reality is forcing a rethink of the fabric itself. The result is ESUN — Ethernet for Scale-Up Networking — an open, OCP-defined effort to evolve Ethernet into a lossless, low-latency, deterministic transport built for the way AI accelerators actually talk to each other.

Fig. 1: AI accelerator clusters need tightly orchestrated interconnects to scale efficiently.

The tail-latency problem: One slow packet stalls the cluster

Classic Ethernet was engineered as a best-effort fabric. It tolerates occasional loss, retries, and jitter because most cloud workloads can absorb them. AI training cannot.

AI performance is gated by tail latency — the slowest packet in a collective operation. Even if 99% of traffic arrives on time, one delayed packet can stall an all-reduce and idle the entire cluster. Packet loss compounds the problem: retransmissions inject additional delay and variability that ripple across synchronized workloads.

At scale, these inefficiencies translate directly into wasted bandwidth, higher power draw, and rising infrastructure cost. When clusters grow to hundreds of thousands of accelerators, the math simply doesn’t hold.

From an architect’s point of view, the goal of a scale-up network is almost the opposite of what Ethernet was built for: the network should disappear. Accelerators should behave as if they’re inside a single, unified machine — communication that feels local rather than remote. That requires a fabric that is not only fast, but predictable, efficient, and tightly coupled to the compute domain.

Where standard Ethernet falls short for scale-up

Ethernet does include congestion tools — PFC and ECN — but these were designed for general-purpose data centers, not the tightly coupled, latency-sensitive traffic patterns of an AI pod. At scale-up distances and data rates, three limitations become structural:

• Protocol overhead. Standard IP headers add 28–48 bytes per packet. In scale-up traffic, where messages are small and frequent, that overhead directly erodes usable throughput.
• No link-level error recovery. Beyond FEC, Ethernet leans on upper-layer transport to recover errors — an approach that costs orders of magnitude in latency.
• Coarse congestion control. PFC is a link-wide pause. It cannot distinguish between traffic classes or virtual channels, which leads to head-of-line blocking exactly when AI workloads can least afford it.

These gaps have pushed some architectures toward proprietary interconnects. Those solve the immediate problem but bring their own baggage: ecosystem fragmentation, reduced flexibility, and long-term vendor risk.

Fig. 2: ESUN vs standard Ethernet: Architectural enhancements.

ESUN: Evolving Ethernet, not replacing it

Rather than starting over, the industry is adapting Ethernet where it needs to change and preserving what already works. That’s the core philosophy behind ESUN.

What stays intact matters as much as what’s new:

• Operational familiarity — network teams keep their existing Ethernet expertise, tooling, and workflows instead of learning a new fabric.
• Infrastructure reuse — scale-up and scale-out traffic share the same switching architecture and physical layer, keeping cost and complexity in check.
• One unified fabric — Ethernet becomes the common connective tissue across the AI data center, from inside the rack to across the campus.

The enhancements themselves are surgical:

• The physical layer remains standard Ethernet.
• The link layer adds lossless reliability and fine-grained congestion control.
• The network layer is streamlined to strip out overhead the scale-up domain doesn’t need.

The net effect: AI systems get Ethernet’s scale, interoperability, and ecosystem economics without inheriting assumptions written for a different era.

A smaller header with outsized impact

The most visible change is at the packet itself. Where standard Ethernet carries 28–48 bytes of IP header overhead, ESUN replaces it with a compact 4-byte header. In a workload dominated by small, frequent messages, that difference translates directly into higher effective bandwidth and lower per-packet latency.

Fig. 3: IP header vs. ESUN header.

Nothing critical is lost in the trim. Traffic prioritization, congestion signaling, and load balancing are all still there — just implemented more efficiently for the scale-up domain.

Engineering for predictable, lossless communication

ESUN introduces two mechanisms that push determinism down into the link layer, where it belongs for scale-up:

• Link-Level Retry (LLR) detects and recovers from link errors locally at the data link layer, rather than punting recovery up the stack. That drops tail latency dramatically and avoids costly end-to-end retransmission.
• Credit-Based Flow Control (CBFC) replaces PFC’s blunt link-wide pause with per-virtual-channel flow control. Senders only transmit when the receiver has confirmed buffer capacity, delivering lossless behavior without head-of-line blocking.

Together, LLR and CBFC give ESUN its signature profile: lossless, low-latency, bandwidth-efficient — with Ethernet’s openness and interoperability intact.

A complete ESUN IP solution

Fig. 4: ESUN solution.

To help SoC teams move from spec to silicon quickly, Synopsys has introduced the industry’s first complete ESUN IP solution spanning both Layer 1 and Layer 2 — a pre-verified stack designed to work together out of the box.

The solution includes:

• 1.6T multi-rate Ethernet MAC — supporting up to four independent 400G channels, configurable for 1×1.6T, 2×800G, 4×400G, and 4×200G modes over 224G SerDes
• 1.6T Ethernet PCS with RS-FEC — RS544 for robust error correction and RS272 for low-latency operation
• UE/ESUN Link Layer Controller — implementing LLR and CBFC for lossless reliability and fine-grained congestion management
• Silicon-proven 224G Ethernet PHY — optimized for low power, latency, and signal integrity
• Comprehensive Verification IP and system-level validation support, including an ESUN-ready SoC Verification Kit (SVK)

By delivering the full stack, Synopsys collapses much of the integration burden — and integration risk — that typically comes with assembling high-speed networking IP from multiple sources.

Built for integration, performance, and scale

• End-to-end integration. MAC, PCS, PHY, and the UE/ESUN Link Layer Controller are co-designed and validated as a single system, eliminating the multi-vendor stitching that so often derails schedules late in a program.
• One architecture for scale-up and scale-out. The same IP addresses both ESUN (scale-up) and Ultra Ethernet (scale-out), letting teams reuse a common architecture across different parts of the data center.
• Optimized for real-world constraints. The solution targets low power, high performance, and area efficiency, with multi-rate configurations from 100G to 1.6T and flexible FEC modes for varied system requirements.
• A proven PHY foundation. At the core is the Synopsys 224G PHY, in production across multiple advanced process nodes. Since October 2022, Synopsys has publicly demonstrated 224G silicon interoperability in more than 30 multi-vendor showings at ECOC and OFC, delivering zero post-FEC errors over channels with up to 45 dB of loss — evidence that what works on paper holds up in silicon.

Looking ahead: A network built for AI

As AI models continue to scale, the demands on the fabric will only intensify. Networks will need to be fast — but also predictable, efficient, and scalable enough to keep hundreds of thousands of accelerators productively busy. Backed by more than 175 companies, including the leading hyperscalers and silicon vendors, ESUN represents the point at which Ethernet converges on that reality.

Synopsys’ ESUN IP solution is one piece of a broader HPC IP portfolio built to support the full AI system stack:

• Scale-up connectivity with ESUN and UALink
• Chip-to-chip connectivity with PCIe and CXL
• Scale-out networking with Ethernet and Ultra Ethernet
• High-bandwidth memory interfaces
• Multi-die and chiplet interconnects
• Security and Foundation IP

Together, these building blocks give architects a foundation where compute, memory, and connectivity scale in lockstep — which is exactly what the next generation of AI infrastructure will demand.

Learn more

• Visit the Synopsys ESUN IP Solution page — full overview of the industry’s first complete L1+L2 ESUN IP.
• Download the ESUN IP Solution datasheet — full architecture, features, and supported configurations.