Shrink Or Package?

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise.

Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced packaging began with IBM flip chips in the 1960s, and it got another boost with multi-chip modules in the 1990s, particularly for the mil/aero market. Still, it never became the first choice of commercial chipmakers because shrinking features was less expensive in terms of silicon area, the ecosystem of tools and IP was well established for scaling, and time-to-profitability was much better defined.

The economics began changing significantly at 16/14nm with the introduction of finFETs and double patterning. Design and manufacturing costs are expected to rise at each new node after that. Shrinking features will require new materials at 5nm for contacts and possibly the interconnects, as well as new transistor structures at either 5nm or 3nm (most likely gate-all-around FETs). And then there is high-numerical-aperture EUV, and new etch, deposition and inspection equipment. Collectively, those steps increase the cost of developing and manufacturing chips at advanced processes at a time when there are fewer market opportunities for chips with high-enough volume to offset the costs.

These factors haven’t exactly been a surprise to the semiconductor industry, although EUV’s continued delays did force design teams to adopt multi-patterning for the metal1 and metal2 layers. Nevertheless, it has taken time to develop viable alternatives, and to prove and refine them. EDA vendors now are offering tools and complete flows to build chips using a variety of packaging options, and there are enough advanced-packaging chips in production in high-visibility markets to prove this option is viable from vendors such as Apple, AMD, Huawei, Cisco, IBM, and Xilinx, as well as such as , high-bandwidth memory (HBM), and the Hybrid Memory Cube.

In addition, two of the largest IDMs—Intel and Samsung—now offer low-cost proprietary bridge technology with their foundry services. And all of the major OSATs are offering one or more versions of fan-out wafer-level packaging, in addition to 2.5D and 3D options. This is reflected in growth among all segments of advanced packaging.

Fig. 1: Advanced packaging revenue by platform, in billions of dollars. Source: Yole Developpement Status of the Advanced Packaging Industry 2017 report, May 2017.

Design automation tools
One of the signs of growth in this market is in automation tools. Of the Big Three EDA vendors,  Cadence was the first to offer packaging tools. The company jumped into the market back in the 1990s, and it has been developing tools since the beginning of the Millennium based upon the observation that analog doesn’t scale. But it has taken nearly 15 years for that vision to migrate into the mainstream and for other EDA vendors to see this as an opportunity worth the R&D investment.

Mentor, a Siemens Business, earlier this month introduced a flow and new tools for advanced packaging, as well. “The process is now similar to the silicon process,” said Keith Felton, product marketing manager for the company’s Advanced IC Packaging solutions Board Systems Division. “We envision multiple design kits will emerge. So you’ll see two kits for fan-out wafer-level packaging, each with slight variations, as well as side-by side, stacked die, chip on wafer on substrate (CoWoS), high-pin-count flip chips and system-in-package.”

Felton says this will work in conjunction with other tools, including DFM tools and the PCB analysis and verification.

“This is all about physics-based simulation,” said John Lee, general manager and vice president at ANSYS. “This is not just about the semiconductor. It’s thermal analysis and mechanical simulation. If you look at TSMC‘s InFO, you have silicon with wafer-level packaging. You need to do simultaneous thermal-level analysis because there are significant physical effects. And that could include 7nm, 10nm, 16nm, or even older process nodes. But the thermal piece affects the reliability of the system. So if you talk about electromigration and you’re not talking about thermal, then you probably have a pessimistic view of the world. And if you have a non-pessimistic view, that can be dangerous.”

, chairman and co-CEO of Synopsys, said the real key is being able to visualize the entire system and to build components and tools that work across a variety of packaging schemes.”So with IP, you have to characterize it so it works under all circumstances. Overall simulations are system simulations, and multiple chips in various forms make up that system. That also includes software. The ability to model and prototype what people build is critical. That includes digital and digital/mixed signal.”

He noted that it also includes emulation and software prototyping. “You need to be able to run software on hardware you don’t have yet,” de Geus said, whether that is in a package or on a 7nm SoC.

But adding these kinds of tools for advanced packaging will go a long way toward adding predictability into those approaches.

“The EDA tools will make a big difference,” said Jan Vardaman, president of TechSearch International. “You can’t do a lot of things without design tools, and going forward we’re going to see increased use. Wherever you can, you want to go with older nodes in a design if you can partition that properly. For that, design tools are sorely needed.”

Packaging strategies
“As products evolve from generation to generation, the methodology from our first generation becomes the norm,” said Ou Li, senior director of engineering at ASE. “As we move forward with advanced products, we can fan out what we learn to the rest of the products. Hopefully, with the learning curve and machine learning and throughput, we can accommodate the rest of these products. So the most advanced products are being supported by volume and business scale. For smaller, more fragmented markets, those kinds of things may not be there. But for the product requirements, it may be easier to implement because we’ve learned this with other products.”

Still, market fragmentation has an impact. As designs become more defined by software—rather than differentiation actually being coded into the software using generic hardware platforms—no two designs are the same and the demands from end customers are much more exacting.

“Each different category of product has a different challenge,” said Li. “But for system in package, we have to meet stringent customer requirements. That is a trend for all types of advanced packaging.”

The next step is to start building platforms so the pieces can be swapped in and out more quickly, adding what has been called a “mass customization” approach using packaging.

“The real opportunity is to be able to integrate everything into a platform,” said Scott Sikorski, vice president of worldwide product marketing at STATS ChipPAC. “That will drive the next level of growth. eWLB (embedded wafer-level ball grid array) is a great opportunity to build something that people are already building in a different way.”

How quickly companies adopt that approach remains to be seen. Fan-outs have been in high demand for the past 18 months, but the capacity for developing those types of devices has been limited. That has recently changed as OSATs have increased their capacity.

“Now there is more capacity to develop a lot more devices, and you’ll see a lot more devices soon,” said Sikorski, noting that packaging as an integration platform is also beginning to gain traction. “This is a very low-cost approach because you already have all of the building blocks. We originally thought this would be a PoP format with a through-via structure around the chip. But at the time we suggested it, the supply chain was not ready.”

The learning curve
One of the big advances over the past few years comes from experience in working with advanced packaging for a variety of markets.

“The people doing packaging, test and DFT are now rock stars” said Mike Gianfagna, vice president of marketing at eSilicon. ” Complexity is growing even with packaging. With 2.5D, you have to think about the silicon substrate, thermal and mechanical stress, and more analysis. So the packaging and DFT teams are involved much earlier and all the way through the development process. DFT can impact the entire schedule.”

The goal is to add more predictability into the design process, which takes time to sort out. However, executives and analysts agree that predictability is improving.

“This is still not routine yet because any new technology or technology node has a learning curve,” said Gianfagna. “On almost every chip we’re doing something for the first time. But we’re doing a better job of identifying issues early and understanding the interaction between the chip, memory, high-performance I/O and the substrate.”

Brandon Wang, engineering group director at Cadence, said that all of the major networking companies now have 2.5D designs in the works. “You’ll see the products rolling out next year,” said Wang. “You’ll also see a lot more sensors, particularly MEMS chips, in packages with other chips. The nature of those designs is very different, though, and until recently many of these designs have been very segmented, so it has been hard to create a methodology for all of this. But the direction is that because sensors are so cheap these are going to be more standardized units. It will be more of a platform approach, so if you need something you can get it very quickly.”

To make that happen requires a multi-die co-design, where the sensor parameters are adjusted at the same time as the rest of the electronics.

“We’re going to have sensors everywhere, and you have to co-optimize them,” said Wang. “It will become more electrical-centric. The electronic designers are still focused on yield for the end device, and the platform will enable them to focus on electrical performance and talk to the sensor platform. Every system will have sensors, but you can design a sensor hub that is optimized for specific use cases. That way if you have five sensors, it’s not five times the price. Maybe it’s only 1.3X. And it’s a standard sensor or a sensor hub, so you know how it’s going to behave.”

The focus on platforms is a key piece of this strategy going forward. It makes it easier to add heterogeneity into designs with more predictable results. But platforms also can greatly reduce the cost of designs because they provide economies of scale and the ability for more companies to compete.

“Customers are looking for more and more guidance from us and design suggestions,” said , senior director of market development at ARM. “Last year we introduced design guidance, but it was not just about the processor. It’s also about performance and power numbers. We also have a pre-built software platform to help them get over traditional hurdles.”

One of the issues is that there is no longer a single best way to accomplish something. While in the past, progress was measured by process node, the emphasis on heterogeneity has greatly increased the number of possible choices. Not everything has to be integrated into a single die, and in many cases IP varies significantly from one foundry to the next even at the same process node.

“We’re now involved with our lead partners on every aspect of design,” said Neifert. “That even includes early RTL, although more typically this is done at the IP level than at the subsystem level. And it now includes everything from safety requirements to security. We’re trying to identify any weak link so that when we tie everything together there is not an underlying problem.”

And this is just the beginning. The rollout of EDA tools and flows will add a whole new level of control in these devices.

“You’ll see greater accuracy, smaller feature sizes, and we will be able to start looking at designs in 3D,” said Mentor’s Felton. “You’ll be able to construct blueprints for ‘what if’ scenarios for substrates and you’ll be able to have chip-level models that will include thermal verification.”

The goal is more upfront analysis of different packaging options, which will become particularly important for choosing substrates, packaging types, IP as well as the interconnects within and between chips.

“There are different user types involved here,” said Felton. “There are IC designers and architects, who are coming up with the package type, which may be die-stack-die or PoP, and then they hand that off to a second team to do the package design. That requires a dedicated solution and flow. It’s moving it from mechanical to EDA.”

Conclusion
After 52 years of Moore’s Law, chip design and manufacturing on a single die is very predictale. The entire ecosystem is in place and it hums like a finely tuned machine. It will take time for advanced packaging to achieve that level of predictability, but there are enough of the kinks worked out of the system today, and enough examples of successful packaging, that it is no longer a huge gamble. And as more tools and predictability are created, pricing will continue to drop for fan-outs and 2.5D implementations.

Most industry insiders believe that a handful of companies will continue to shrink logic at the most advanced nodes, but increasingly they will add more elements into a package around that logic. The future is heterogeneous, and the easiest way to mix those elements will be inside a package, not on a single die.

Related Stories
Architecture First, Node Second
Even the biggest proponents of scaling have changed their tune.
Inside FD-SOI And Scaling
GlobalFoundries’ CTO opens up on FD-SOI, 7nm finFETs, and what’s next in scaling.
Moore’s Law: Toward SW-Defined Hardware
Part 2: Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.