One-on-One: Naoya Hayashi

By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the current and future challenges in the photomask industry with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). SE: What are the big challenges for the photomask industry today? Hayashi: There are several challenges. Most of the challenges involve mask complexity. It is also quite difficult to handle the mask data, because it is ... » read more

FinFET Reliability Issues

By Arvind Vel - 13 Mar, 2014 - Comments: 0

The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

Interconnect Challenges Grow

By Mark LaPedus - 20 Feb, 2014 - Comments: 0

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

What’s After CMOS?

By Mark LaPedus - 24 Jan, 2014 - Comments: 3

Chipmakers continue to scale the CMOS transistor to finer geometries, but the question is for how much longer. The current thinking is that the CMOS transistor could scale at least to the 3nm node in the 2021 timeframe. And then, CMOS could run out of gas, prompting the need for a new switch technology. So what’s after the CMOS-based transistor? Carbon nanotubes and graphene get the most a... » read more

Executive Viewpoint: Qualcomm On Process Technology

By Mark LaPedus - 23 Jan, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future process technology challenges with Geoffrey Yeap, vice president of technology at Qualcomm. SE: You have pointed out there is a fundamental shift taking place at the 28nm logic node. This is the first node in which mobile chips have been ramped up first within the foundries, ahead of computing-based ICs. Many believe that 28nm ... » read more

Germanium wedge-FETs pry away misfit dislocations

By Katherine Derbyshire - 23 Jan, 2014 - Comments: 1

Any approach to alternative channel integration must consider the lattice mismatch between silicon and other channel materials. Some schemes, such as IMEC’s selective epitaxy, view the lattice mismatch as an obstacle and look for ways to minimize its effects. This point of view certainly has merit: misfit dislocations do significantly degrade transistor performance. Still, back in 2011 Shu-Ha... » read more

Routing Closure Challenges At 28nm And Below

By Jean-Marie Brunet - 03 Jan, 2014 - Comments: 1

As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more

Industry Restructures Around Cost

By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

Different Economies Of Scale, And Lots Of Questions

By Ed Sperling - 12 Dec, 2013 - Comments: 0

Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair. The argument being presented is that economies of scale will still exist for those companies with pockets deep enough ... » read more

Can Intel Dethrone The Foundry Giants?

By Mark LaPedus - 12 Dec, 2013 - Comments: 3

The leading-edge foundry business isn’t for the faint of heart. It requires deep pockets and sound technology to keep pace in the chip-scaling race. And despite pouring billions of dollars into new fabs and processes, foundries are competing for fewer customers at each node. Given the difficult business conditions, only a handful of vendors can afford to compete in the high-end foundry bus... » read more

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