tag: Real Intent

Will 2026 Be Dominated By AI?
By Brian Bailey - 15 Jan, 2026 - Comments: 0

Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

2025 – A Year Of Change And Anticipation
By Brian Bailey - 23 Dec, 2025 - Comments: 0

2025 has certainly been a year of unexpected changes. These had a significant impact on the semiconductor industry and everything that supports it. Not all the changes have been bad, but flexibility has been a requirement for continued success or to make the most of an opportunity provided. Some industries, such as aerospace and defense, are seeing a significant boost around the world. Data ... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Is There Any Hope For Asynchronous Design?
By Brian Bailey - 25 Apr, 2024 - Comments: 6

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet has never resulted in more than a few experiments. Synchronous design utilizes a clock, where the clock frequency is set by the longest and slowest path in the design. That includes potential var... » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

EDA Back On Investors’ Radar
By Brian Bailey - 25 Jan, 2024 - Comments: 0

EDA is transforming from a staid but strategic sector into a hot investment market, fueled by strong earnings and growth, a clamoring for leading-edge and increasingly customized designs across new and existing markets, and the rollout of advanced technologies such as AI for a range of tools that will be needed to develop new architectures with much greater performance per watt. A confluence... » read more

2023: A Good Year For Semiconductors
By Brian Bailey - 21 Dec, 2023 - Comments: 0

Looking back, 2023 has had more than its fair share of surprises, but who were the winners and losers? The good news is that by the end of the year, almost everyone was happy. That is not how we exited 2022, where there was overcapacity, inventories had built up in many parts of the industry, and few sectors — apart from data centers — were seeing much growth. The supposed new leaders we... » read more

Challenges Grow For Data Management And Sharing In EDA
By Ed Sperling - 29 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about more openness in EDA data, how increased complexity is affecting time to working silicon, and the impact of geopolitics, with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business U... » read more

CEO Outlook: Chiplets, Data Management, And Reliability
By Ed Sperling - 14 Jun, 2023 - Comments: 0

Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

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