tag: Cadence

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Blog Review: March 2
By Jesse Allen - 02 Mar, 2016 - Comments: 0

Ansys' Bill Vandermark test drives the potential downsides of autonomous cars in his top tech articles of the week. Plus, the world's first fully robotic lettuce farm and big improvements for old technology. Synopsys' Graham Etchells takes a look at what makes FinFET layout methodology different and how 'smart' PCells can help. Mentor's John Day introduces the Open Lab Alliance, a group o... » read more

Preparing For The IoT Data Tsunami
By Ann Mutschler - 29 Feb, 2016 - Comments: 0

Engineering teams are facing a flood of data that will be generated by the [getkc id="76" comment="Internet of Things"], both from the chip design side and from the infrastructure required to handle that data. There are several factors that make this problem particularly difficult to deal with. First, there is no single data type, which means data has to be translated somehow into a usable f... » read more

The Week In Review: Design/IoT
By Jesse Allen - 26 Feb, 2016 - Comments: 0

Tools Synopsys incorporated automated analog and mixed-signal debug capabilities into its Verdi SoC debug platform, which now provides comprehensive hierarchical and schematic views of both the analog and digital portions of designs and automated tracing across analog and digital blocks. Mentor announced three applications for the Veloce emulation platform focused on overcoming unpredicta... » read more

Racing To Design Chips Faster
By Ed Sperling - 25 Feb, 2016 - Comments: 6

A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

IP Requirements Changing
By Brian Bailey - 25 Feb, 2016 - Comments: 0

Twenty years ago the electronics industry became interested in the notion of formalizing re-use through third-party IP. It has turned out to be harder than anyone imagined. In 1996, the Virtual Socket Interface Alliance ([getentity id="22845" comment="VSIA"]) was formed to standardize the development, distribution and licensing of IP. Soon afterward, companies with a couple of people in a ga... » read more

Masters Of Abstraction
By Ann Mutschler - 25 Feb, 2016 - Comments: 0

Good system designers are a unique breed. While it's easy enough to distinguish the traits that define a good one from a weak one, it's much harder to determine who possesses those traits before they are put to the test, or whether or how they can be taught. However, there is definitely a particular perspective that good system designers hold in common. The key is the ability to work with ma... » read more

Getting Formal About Debug
By Brian Bailey - 25 Feb, 2016 - Comments: 0

While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

Education And Communication
By Frank Schirrmeister - 25 Feb, 2016 - Comments: 0

With the System Development Suite introduced back in 2011, it is worthwhile to review how the adoption of the connected verification engines has progressed. It turns out that only part of the issues to be solved are purely technical. Communication across different technology areas is key, and with that, education of a new breed of engineer may become a key issue going forward. As a son of a ... » read more

Blog Review: Feb. 24
By Jesse Allen - 24 Feb, 2016 - Comments: 0

Synopsys' Graham Etchells digs through the toolbox and finds that schematic PCells can be vital in helping layout engineers tackle FinFET complexity. Cadence's Paul McLellan looks at two techniques to test the increasing number of digital gates on an automotive chip with only two pins. In the latest PCB Tech Talk Podcast, Mentor's John McMillan discusses where collaboration with MCAD fits... » read more

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