Are More Processor Cores Better?


Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Another Tool In The Bag


Clocks can account for 25% to 40% of total dynamic power consumption in a complex chip, so when looking for areas to reduce power, the clock tree network is a good place to start. Structurally, it is certainly possible to have single-bit flip flops with a clock that connects to every one of the flip flops, and the power in general is proportional to the number of buffers in the clock tree on... » read more

The Multicore Processing Conundrum


We drive relentlessly into our technological future and often it seems like we’re upgrading our high-performance vehicle as it speeds forward. That’s no easy task, to be sure. We were roaring along fine, observing Moore’s Law, and then we hit a speed bump. So design teams quickly adopted multi-core designs to compensate for the fact that pushing up speeds on single-core CPUs was a melt... » read more

The Week In Review: Design/IoT


Chips NXP rolled out what it claims are the most power-efficient microcontrollers for always-on applications. The minimum draw is 3 microamps for continuous sensor listening. Tools Mentor Graphics beefed up its CFD tool, adding thermo-fluid analysis simulation capabilities for automotive, aerospace and industrial applications. Included is support for FMI, an open-source environment that al... » read more

Virtual Prototyping Takes Off


Semiconductor Engineering sat down with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer Solutions at [getentity id="22035" e_name="Synopsys"]; Larry... » read more

Keeping Up With The Productivity Challenge


Until recently, EDA software rode the coattails of increasing processor performance as part of its drive to continue providing faster and more powerful development software to the people designing, among other things, the next generation of faster processors. It was a fortuitous ring. Around the turn of the century, with the migration to multi-core computing systems, all of that changed. In ord... » read more

A Formally Free Lunch


I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

Blog Review: Nov. 5


Cadence's Brian Fuller zeroes in on ISO 26262, the automotive safety standard that's supposed to guard against nightmare failures in your car. Hopefully it works. They won't protect against cyber terrorism, though. Rambus' Aharon Etengoff takes a look at the challenges of connected vehicles. Mentor's J. Van Domelen looks at NASA's increased reliance on commercial partners, which has not b... » read more

The Week In Review: Design


Tools Mentor Graphics rolled out an extension to its PCB design platform that allows for synchronization of processes across multi-board systems. The new tool captures logic and system definitions for boards, cables, backplanes, cable assemblies, sensors and actuators. Cadence introduced a dynamic characterization solution for mixed signal blocks such as PLLs, data converters, high-speed tr... » read more

Are Models Holding Back New Methodologies?


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirrmeister, group director... » read more

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