Supporting LP In New Process Nodes


Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

Experts At The Table: FinFET Questions And Issues


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

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