Utilizing More Data To Improve Chip Design


Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Formal Signoff


Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

Tech Talk: Better Coverage


Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

Measuring Verification Accuracy


[getkc id="10" kc_name="Verification"] is the unbounded challenge that continues to confound engineering teams across the globe, who want to know when "enough" is "good enough" to proceed to tapeout. The answer is not straightforward, and it includes more variables than in the past, particularly around power. Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor ... » read more