tag: Coventor

Speeding Up Process Optimization With Virtual Processing
By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

Atomic Layer Etch Expands To New Markets
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

The semiconductor industry is developing the next wave of applications for atomic layer etch (ALE), hoping to get a foothold in some new and emerging markets. ALE, a next-generation etch technology that removes materials at the atomic scale, is one of several tools used to process advanced devices in a fab. ALE moved into production for select applications around 2016, although the technolog... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
By Coventor - 17 Jun, 2020 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)
By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication
By Coventor - 01 Jun, 2020 - Comments: 0

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more

EUV’s Uncertain Future At 3nm And Below
By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

New Uses For Manufacturing Data
By Ed Sperling - 12 May, 2020 - Comments: 0

The semiconductor industry is becoming more reliant on data analytics to ensure that a chip will work as expected over its projected lifetime, but that data is frequently inconsistent or incomplete, and some of the most useful data is being hoarded by companies for competitive reasons. The volume of data is rising at each new process node, where there are simply more things to keep track of,... » read more

Identifying And Preventing Process Failures At 7nm
By Qingpeng Wang - 20 Apr, 2020 - Comments: 0

Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Big Changes In Tiny Interconnects
By Ed Sperling - 16 Apr, 2020 - Comments: 1

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

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