Multi-Patterning Issues At 7nm, 5nm

By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill

By Mentor, a Siemens Business - 19 Oct, 2016 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Capacity Constraints And DFM At Mature Nodes

By Jeff Wilson - 19 Mar, 2015 - Comments: 0

We’re witnessing an interesting phenomenon in the SoC segment of the semiconductor industry today. One might call it the “forced waterfall effect.” What I’m referring to is the tendency for production at semiconductor nodes older than the leading edge to be under long-term foundry capacity constraints. Normally this occurs with the “hot process node,” that is, the leading edge wh... » read more

Fill Database Management Strategies At Advanced Nodes

By Jeff Wilson - 13 Nov, 2014 - Comments: 0

Fill has been around for many nodes, and was originally introduced to improve manufacturing results. The foundries learned that by managing density they were able to reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes, so they introduced density design rule checks (DRC). To meet these density requirements, designers “filled” open areas of the layou... » read more

A Guide To Advanced Process Design Kits

By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Enabling Test Portability With Graphs

By Ann Mutschler - 20 Mar, 2014 - Comments: 0

Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more

It’s A Materials World

By Mark LaPedus - 15 Aug, 2013 - Comments: 0

By Mark LaPedus At a recent event, Intel’s fab materials guru described a nightmarish occurrence that nearly brought the chip giant to its knees. Tim Hendry, director of fab materials and vice president of the Technology and Manufacturing Group at Intel, said the company obtained a critical material from an undisclosed supplier. “This large sub-supplier, a very large chemical company, m... » read more

Let’s All Meet At The Via Bar!

By Jean-Marie Brunet - 30 Jun, 2013 - Comments: 0

By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

Challenges Of Physical Design Closure

By Jean-Marie Brunet - 22 Oct, 2012 - Comments: 0

By Jean-Marie Brunet A clear trend in IC design is that with each smaller process node, reaching design closure gets more difficult, expensive, and time consuming. Printing ever-smaller features with 193nm wavelength light has introduced unprecedented levels of manufacturing challenges, which are addressed with a growing set of complex design rules (DRC) and design for manufacturing (DFM) cons... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: design for manufacturing