tag: EDA

Custom Designs, Custom Problems
By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Analog Chip Layout: Creativity Vs. Deadlines
By Benjamin Prautsch - 10 Sep, 2020 - Comments: 0

The entire design of integrated circuits, from the specification onward, depends on successful validation by measurement of microchips. One key milestone in this process is the completion of the layout. However, the path to reach this point can be quite difficult as many iterations are usually required. It includes: Iterations with the customer to finalize the specification. Iteratio... » read more

Optimizing For Energy In Physical Design
By Pierre-Alexandre Bou-Ach - 10 Sep, 2020 - Comments: 0

Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies. Predictions show that the energy of electronics may soon consume 20% to 33% of the global energy supply, as it is highlighted in this blog post about "Design and Manufacturing in 2030" from Greg Yeric, fellow at Arm. Energy efficiency is such an important global issue that it is ... » read more

Components For Open-Source Verification
By Brian Bailey - 02 Sep, 2020 - Comments: 2

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term. Part one examined the reasons why open-source... » read more

Artificial Intelligence And Machine Learning Add New Capabilities to Traditional RF EDA Tools
By Cadence - 26 Aug, 2020 - Comments: 0

This article features contributions from RF EDA vendors on their various capabilities for artificial intelligence and machine learning. AWR Design Environment software is featured and highlights the network synthesis wizard. Click here to continue reading. » read more

From Cloud To Cloudlets
By Ed Sperling - 17 Aug, 2020 - Comments: 0

Cloudlets, or mini-clouds, are starting to roll out closer to the sources of data in an effort to reduce latency and improve overall processing performance. But as this approach gains steam, it also is creating some new challenges involving data distribution, storage and security. The growing popularity of distributed clouds is a recognition that the cloud model has limitations. Sending the ... » read more

Astera Labs: Purpose-Built Connectivity
By Ed Sperling - 14 Aug, 2020 - Comments: 0

Growing amounts of data are forcing companies to rethink where data is processed and when, how and where it is moved. But solutions may vary greatly from one company to the next, and from one use case or application to the next. This is forcing the adoption of a heterogenous compute architecture that combines traditional processors, such as CPUs, GPUs and FPGAs, with AI processors and smart net... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

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