Methodology Shifts Ahead


By Pallab Chatterjee The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design. Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushe... » read more

Where Do We Go Next?


Jim Hogan and Paul McLellan opened an interactive, thought-provoking discussion at ICCAD this week on how EDA needs to change to be successful in the year 2020. The conclusion of this well-known duo--Hogan, the VC, and McLellan, the blogger, in their current incarnations--pointed toward optimization and software signoff, given the amount of software that is now moving into designs and t... » read more

What The Downturn Has Wrought


!--StartFragment--> The big companies felt the pain first, or at least they acknowledged it. In big companies, pain is felt in dollars. In smaller companies, it’s felt everywhere because every person counts. What the big IDMs did first was offload their fabs, or at least open them up for enough business to sustain their investments in new technology. That’s the strategy taken by IBM, an... » read more

Who’s Out, Who’s In


The EDA world is either doing better than most segments of the economy or coming apart at the seams, depending upon your perspective and your definition of exactly what an EDA company is. But at least one trend seems clear: As we push into the world of system-level design from chip design and SoCs instead of ASICs, the high-level trend is broader companies with more complete integrated packag... » read more

The ESL Conundrum


As Moore’s Law continues its relentless march, the “electronic system level” (ESL), which is the next higher level of abstraction above the register transfer level (RTL), continues to be adopted as an answer to the ever-increasing complexity of designing semiconductors. Although ESL emerged about five years ago, the term itself still can confound the very community that seeks to embrac... » read more

Quality time?


By Ed Sperling System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional design and verification tools and methodology manager at Freescale; Kelly Larson, design verification engineering manager at MediaTek Wireless; Adnan Hamid, CEO of Breker, and ... » read more

Cross-Talking with TLM 2.0


By Ed Sperling It’s almost like flying over the Great Plains of the United States. On the ground it’s hard to see above the corn stalks, but in an airplane you can see the entire horizon even if you can’t see those stalks anymore. The analogy is similar to where most of the major players in chip design say the engineering for systems on chips needs to go. With millions more gates avai... » read more

New Challenges For Hardware Engineers


  It used to be fun to be a chip architect. You could wake up in the morning, grab a cup of strong black coffee and run through a few power and performance tradeoff calculations before deciding on the high-level architecture. That would set the engineering direction for months, if not years. On a good day, after introducing a steady infusion of caffeine into your bloodstream, you felt like ... » read more

Engineering Schools Trail Chip Design Changes


Complexity in designing chips is relatively well understood, even if it’s not easy to solve the problems and actually create the chips. But engineering schools are only beginning to grasp the enormity of the change, and their curricula are running years behind what is happening in the industry.   Corporations have spent years tearing down silos, and technology has forced the same kinds o... » read more

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