tag: heterogeneous integration

The Chip Industry’s Next-Gen Roadmap
By Mark LaPedus - 21 Jan, 2021 - Comments: 1

Todd Younkin, the new president and chief executive of the Semiconductor Research Corp. (SRC), sat down with Semiconductor Engineering to talk about engineering careers, R&D trends and what’s ahead for chip technologies over the next decade. What follows are excerpts of that conversation. SE: As a U.S.-based chip consortium, what is SRC's charter? Younkin: The Semiconductor Research... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last
By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

LDFO SiP For Wearables & IoT With Heterogeneous Integration
By Amkor - 02 Dec, 2020 - Comments: 0

Authors A. Martins*, M. Pinheiro*, A. F. Ferreira*, R. Almeida*, F. Matos*, J. Oliveira*, Eoin O´Toole*, H. M. Santos†, M. C. Monteiro‡, H. Gamboa‡, R. P. Silva* ‡Fraunhofer Portugal AICOS, Porto, Portugal †INESC TEC *AMKOR Technology Portugal, S.A. ABSTRACT The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the require... » read more

Versal Premium ACAPs: Breakthrough Integration of Networked IP On A Power-Optimized, Adaptable Platform
By Xilinx - 01 Dec, 2020 - Comments: 0

In every market across the world, continuous demand for higher bandwidth metro and core networks scales beyond what today's technologies can support. Data center-centric scientific, enterprise, and consumer applications demand more efficient, higher performance compute that scales beyond what traditional technologies can match. Discrete solutions cannot meet performance, thermal, and bandwidth ... » read more

Emerging Apps And Challenges For Packaging
By Mark LaPedus - 23 Nov, 2020 - Comments: 0

Advanced packaging is playing a bigger role and becoming a more viable option to develop new system-level chip designs, but it also presents chipmakers with a confusing array of options and sometimes a hefty price tag. Automotive, servers, smartphones and other systems have embraced advanced packaging in one form or another. For other applications, it's overkill, and a simpler commodity pack... » read more

How Secure Is The Package?
By Ed Sperling - 17 Sep, 2020 - Comments: 1

Advanced packaging is a viable way of extending the benefits of Moore's Law without the excessive cost of shrinking everything to fit on a single die, but it also raises some issues about security for which there are no clear answers at the moment. OSATs and foundries have been working the kinks out of how to put the pieces together in the most cost-effective and reliable way for the better ... » read more

Advanced Packaging, Heterogeneous Integration And Test
By FormFactor - 11 Aug, 2020 - Comments: 0

Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test. At this exciting time in the industry, open engagement between customers and suppliers has never been more important for the test community. Click here to read more. » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Copper Electrodeposition For Fan-Out Wafer-Level Packaging
By Lam Research - 16 Jul, 2020 - Comments: 0

As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased acceptance is high density fan-out wafer-level packaging (FOWL... » read more

‘More Than Moore’ Reality Check
By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

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