tag: heterogeneous integration

Is This The Year Of The Chiplet?
By Ed Sperling - 23 Jan, 2020 - Comments: 2

Customizing chips by choosing pre-characterized — and most likely hardened IP — from a menu of options appears to be gaining ground. It's rare to go to a conference these days without hearing chiplets being mentioned. At a time when end markets are splintering and more designs are unique, chiplets are viewed as a way to rapidly build a device using exactly what is required for a particul... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

The Problem With Post-Silicon Debug
By Ann Mutschler - 28 Feb, 2019 - Comments: 0

Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Unsticking Moore’s Law
By Ed Sperling - 04 Feb, 2019 - Comments: 2

Sanjay Natarajan, corporate vice president at Applied Materials with responsibility for transistor, interconnect and memory solutions, sat down with Semiconductor Engineering to talk about variation, Moore's Law, the impact of new materials such as cobalt, and different memory architectures and approaches. What follows are excerpts of that conversation. SE: Reliability is becoming more of an... » read more

Packaging Biz Faces Challenges in 2019
By Mark LaPedus - 10 Dec, 2018 - Comments: 0

The IC packaging industry is bracing for slower growth, if not uncertainty, in 2019, even though advanced packaging remains a bright spot in the market. Generally, IC packaging houses saw strong demand in the first part of 2018, but the market cooled in the second half of the year due to a slowdown in memory. Going forward, the slower IC packaging market is expected to extend into the first ... » read more

Sorting Out Packaging Options
By Ed Sperling - 10 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Butler, executive vice president and general manager of SPTS Technologies; Ingu Yin Chang, senior vice president president at ASE Group; Hubert Karl Lakner, executive director of the Fraunhofer Institute for Photonic Microsystems; Robert Lo, division director for electronics and optoelectronics research at Industrial Te... » read more

The Financial Justification For System-Level Test
By Astronics - 23 Jul, 2018 - Comments: 0

Three unique trends are currently transforming high-volume manufacturing in the semiconductor industry: The increasing complexity of chip architectures (e.g., FinFET, heterogeneous integration); The explosion in the breadth and ubiquity of consumer electronics (e.g. IoT, mobile, and automotive), and Consumer expectations of a constant stream of newer, cheaper, more advanced nodes. ... » read more

Tech Talk: Shrink Vs. Package
By Ed Sperling - 10 May, 2018 - Comments: 0

Andy Heinig, group manager for system integration at Fraunhofer EAS, talks about the tradeoffs between planar design and advanced packaging, including different types of interposers, chiplets and thermal issues. https://youtu.be/1BDqgCujJno » read more

Tech Talk: EM Crosstalk
By Ed Sperling - 14 Dec, 2017 - Comments: 0

Anand Raman, senior director at Helic, talks about the impact of electromagnetic interference on digital design at 10/7nm and beyond. Once confined to the analog space, noise is suddenly an issue at advanced nodes for all designs. At the root of the problem are smaller nodes, increased speed and higher levels of integration. https://youtu.be/hzZqK2lNJNQ » read more

Getting Power Management Right
By Ann Mutschler - 14 Nov, 2017 - Comments: 0

Getting power management right in the era of heterogeneous SoCs is a multi-pronged effort, there's no getting around it. Engineering teams daily try to squeeze more and more power from their designs, which many times includes adding human resources and expertise to the project. Take an example where a design team leader gets the mandate to include high level synthesis in the design metho... » read more

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