industry collaboration Semiconductor Engineering

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

by Ed Sperling

Flash Getting Stacked High-Bandwidth Version

Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.

by Bryon Moyer

AI Accelerator Testing Depends On DFT Innovations

Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.

by Laura Peters

Chiplets Need A New Workflow

Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.

by Ann Mutschler

HBM Shifts Testing Left To Preserve AI Chip Yield

Testing sooner and more often can improve quality and reduce scrap, but it's also more costly.

by Anne Meixner

Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

by Liz Allan

Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate