tag: Inpria Corporation

Chip Industry Week in Review

By The SE Staff - 19 Sep, 2025 - Comments: 0

Amkor, TSMC, and Cadence partnered with Tesoro VC, which will serve as the lead operator of a new Global AI + Semiconductor Startup Hub and a Global Design Center in Phoenix, Arizona, aimed at chip innovation, startup growth, and advanced manufacturing. Nvidia will invest $5 billion in Intel common stock at a purchase price of $23.28 per share and the companies will collaborate on AI infrastru... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 Sep, 2021 - Comments: 0

U.S. government officials met with semiconductor industry companies and automakers to request supply chain information it hopes could address the current semiconductor shortage, Reuters reports. Secretary of Commerce Gina Raimondo hopes the information will enable them and industry to "get more granular into the bottlenecks and then ultimately predict challenges before they happen," but also wa... » read more

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The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

Chip Industry Week In Review

AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.

by The SE Staff

Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

by The SE Staff

Toward Agentic Verification

Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?

by Brian Bailey

Swapping Out Chiplets: I/Os Vs. Compute

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?

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Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

by Ed Sperling

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

by Laura Peters

TSMC Tech Symposium 2026, By The Numbers

Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.

by Barry Pangrle

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