Cymer’s EUV Team Has An Exciting Few Months


By Michael P.C. Watts At SPIE Advanced Lithography, Cymer announced some serious progress in EUV source development, one of several highlights. The latest results provided 40W of power in runs over 8 hours that mimicked full productions conditions including dose control. As far as I can tell, 40w translates to around 30 - 300 mm wafers an hour. The Cymer source uses a CO2 laser with 3 ampli... » read more

Extreme sources, block copolymers, and resist polishing at SPIE Advanced Lithography.


by Michael P.C. Watts Lots to talk about from SPIE Advance Lithography Conference this year; EUV power, multi-beam systems, double patterning, and imprint. I thought I would pick up some highlights here, and then come back and talk about them in detail over the next few weeks. One of the extreme sources was the paper from Cymer/ASML on EUV sources . Their paper showed performance, at prod... » read more

SPIE Advanced Lithography 2013 – day 0


Welcome to San Jose and the beginning of the Advanced Lithography Symposium.  The last year seemed to zip by in hurry, and it was an interesting one.  The lithography year 2012 was dominated by two big stories:  progress in directed self assembly (DSA) and lack of progress in Extreme Ultraviolet (EUV) lithography.  I’m anxious to hear the progress reports for each this week.  For EUV, de... » read more

Inflection Points And Changes Ahead


It’s hard to justify throwing away a well-oiled machine and replacing it with a new one. It works, it’s predictable and it’s low risk. And nowhere is this more evident than in the semiconductor industry. The doubling of transistors every two years for nearly five decades has created a $300 billion chip industry, reduced the price of processing by orders of magnitude, and made possible ele... » read more

Optical Lithography, Take Two


By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

A Call To Action: How 20nm Will Change IC Design


The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a �... » read more

Uncommon Goals


I had the opportunity to attend the Common Platform event recently. This is a technology and business showcase sponsored by Global Foundries, IBM and Samsung with major support from ARM, Cadence, Synopsys and Mentor. Wow, that’s some serious sponsorship. The event was well run and provided a good balance of technology details and business outlook. The wine at the evening reception was decent ... » read more

Tech Talk: Getting To The Next Node


IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

Increasing Levels Of Risk


Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

Why Do My DP Colors Keep Changing?


By David Abercrombie At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. The designer only has to verify that the design can be decomposed before taping out each single layer. There are certain obvious advantages to this flow. For example, the designer do... » read more

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