tag: lithography

450mm: Out Of Sync
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time. In one possible scenario, 450mm fabs are projected ... » read more

Manufacturing Bits: July 9
By Mark LaPedus - 09 Jul, 2013 - Comments: 0

Fishy Robots National University of Singapore (NUS) has developed a robotic fish that mimics the movements of a carp—a technology that could pave the way for more efficient autonomous underwater vehicles. This robot is classified as an autonomous underwater vehicle (AUV). Applications include military, pipeline leakage detection, and the laying of communication cable. The robot could be u... » read more

Foundry Talk
By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

Merchant Photomask Makers Remain Relevant
By Jeff Chappell - 20 Jun, 2013 - Comments: 0

By Jeff Chappell For many years the trend in the semiconductor industry with regard to photomasks and chipmakers was to shed captive mask operations in favor of merchant photomask suppliers. This reflected a larger trend all along the supply chain with many companies moving away from vertical integration as, consequently, the foundry model grew. "This was mainly driven by cost consideratio... » read more

Inside Leti’s Litho Lab
By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti. SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam ... » read more

Trickle Down Equipment Economics
By Jeff Chappell - 16 May, 2013 - Comments: 0

By Jeff Chappell By now, with the rise of China as a center of manufacturing, everyone in the chip industry has no doubt heard of the supposed Chinese curse, "May you live in interesting times." It's practically cliché. The thing is, the next two industry cycles may indeed prove interesting for the used equipment market. At the moment, everyone is tired of interesting times, and those in ... » read more

EUV Flare And Proximity Modeling And Model-Based Correction
By Various Writers - 16 May, 2013 - Comments: 0

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in seve... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Experts At The Table: Issues In Metrology And Inspection
By Mark LaPedus - 29 Apr, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing f... » read more

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