tag: Marvell

Week In Review: Design, Low Power
By Jesse Allen - 13 May, 2022 - Comments: 0

Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

Increasing Performance With Data Acceleration
By Martha DeGrasse - 14 Apr, 2022 - Comments: 0

Increasing demand for functions that require a relatively high level of acceleration per unit of data is providing a foothold for in-line accelerator cards, which could mean new opportunities for some vendors and a potential threat for others. For years, either CPUs, or CPUs with FPGA accelerators, met most market needs. But the rapid increase in the volume of data everywhere, coupled with t... » read more

Chiplets Enter The Supercomputer Race
By Mark LaPedus - 17 Mar, 2022 - Comments: 0

Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Mar, 2022 - Comments: 0

Intellectual Property Flex Logix inked an agreement with the Air Force Research Laboratory, Sensors Directorate (AFRL/RY) covering any Flex Logix IP technology for use in all US Government-funded programs for research and prototyping purposes with no license fees. “Our first license with AFRL for EFLX eFPGA in GlobalFoundries 12nm process was highly successful, with more than a half dozen pr... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Mar, 2022 - Comments: 0

Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Which Processor Is Best?
By Ed Sperling - 01 Mar, 2022 - Comments: 2

Intel's embrace of RISC-V represents a landmark shift in the processor world. It's a recognition that no single company can own the data center anymore, upending a revenue model that has persisted since the earliest days of computing. Intel gained traction in that market in the early 1990s with the explosion of commodity servers, but its role is changing as processors become more customized and... » read more

Data Center Architectures In Flux
By Ann Mutschler - 24 Feb, 2022 - Comments: 0

Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Transistors Reach Tipping Point At 3nm
By Mark LaPedus - 23 Feb, 2022 - Comments: 1

The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

Design Challenges Increasing For Mixed-Die Packages
By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Oct, 2021 - Comments: 0

Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy