tag: multi-die assemblies

Resistance In Advanced Packages Is Now A System-Level Problem
By Gregory Haley - 10 Feb, 2026 - Comments: 0

Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Why Move To 2nm?
By Ed Sperling - 04 Feb, 2026 - Comments: 0

Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

Challenges In Moving Data In Chips
By Ed Sperling - 14 Jan, 2026 - Comments: 0

The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they're supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Secure Data Sharing Becoming Critical For Chip Manufacturing
By Laura Peters - 13 Jan, 2026 - Comments: 0

Semiconductor companies increasingly need to share data to solve problems faster, boost yield, and trace the root cause of failed devices. But to make that work, companies need assurances that their data will be secure, free from data leaks that could result in the loss of valuable IP. Data sharing is becoming critical at leading device nodes, where process variability is starting to consume... » read more

Is End-To-End Security Possible?
By Ed Sperling - 08 Jan, 2026 - Comments: 0

Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

AI Buildout Makes HPC Simulation More Challenging
By Ann Mutschler - 11 Dec, 2025 - Comments: 0

Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

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