tag: multi-die assemblies

AI-Driven Collaboration In Chip Manufacturing
By Ed Sperling - 24 Nov, 2025 - Comments: 0

3D chips and multi-die assemblies can offer significant improvements in performance and power, but the tradeoff is the increased amount of time and money it takes to generate working silicon. There are more process steps, more interactions between processes, and more data to manage throughout the manufacturing flow — so much, in fact, that it has now reached well beyond what even the best eng... » read more

Changes In Mixed-Signal IC Verification
By Ed Sperling - 19 Nov, 2025 - Comments: 0

Analog and digital engineers traditionally have worked in very different worlds. Many analog engineers for years have opted to verify analog designs by scrutinizing waveforms, while digital engineers have treated analog blocks like black boxes. But as these two areas converge in advanced SoCs and multi-die assemblies, the demarcation line between these engineering disciplines is being erased. S... » read more

Using AI/ML To Find And Correlate IC Test Data
By Ed Sperling - 15 Oct, 2025 - Comments: 0

What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

Issues In Ramping Advanced Packaging
By Ed Sperling - 05 Aug, 2025 - Comments: 0

Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entir... » read more

Novel Assembly Approaches For 3D Device Stacks
By Laura Peters - 30 Jun, 2025 - Comments: 0

The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Multi-Die Assemblies Complicate Parasitic Extraction
By Ann Mutschler - 12 Jun, 2025 - Comments: 0

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 2

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

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