The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
Chip Industry Week In Review
AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
Chip Industry Week In Review
Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.
Toward Agentic Verification
Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
CPO Is Extending The Limits Of What’s Possible In AI Data Centers
Co-packaged optics technology will have a big impact on system power and the cost of data movement.
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
HBM4E Raises The Bar For AI Memory Bandwidth
The speed at which accelerators can be fed with data has become just as critical as raw compute capability.
Scale Up, Scale Out Get a New Partner
For reaching farther into another data center, developers are now talking about scale-across.
AI Power on the Edge
Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It's a hardware/software/model co-development problem.
Gates Add Functionality, But Wires Create Problems
Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
